From 0678dd8ec738f381f8365e8c1473d070f0ee6b82 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 12 May 2020 19:25:13 +0200
Subject: testsuite/synth: add a test for #1302

---
 testsuite/synth/issue1302/testcase3.vhdl | 25 +++++++++++++++++++++++++
 testsuite/synth/issue1302/testsuite.sh   | 10 ++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 testsuite/synth/issue1302/testcase3.vhdl
 create mode 100755 testsuite/synth/issue1302/testsuite.sh

diff --git a/testsuite/synth/issue1302/testcase3.vhdl b/testsuite/synth/issue1302/testcase3.vhdl
new file mode 100644
index 000000000..48c46af34
--- /dev/null
+++ b/testsuite/synth/issue1302/testcase3.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase3 is
+   generic (
+             edge    : std_logic := '1'
+           );
+   port (
+          clk    : in  std_logic;
+          D      : in  std_logic;
+          Q      : out std_logic
+        );
+end testcase3;
+
+architecture behavior of testcase3 is
+begin
+
+tc3: process(clk)
+     begin
+        if (clk'event and clk=edge) then
+           Q    <= D;
+        end if;
+     end process;
+
+end behavior;
diff --git a/testsuite/synth/issue1302/testsuite.sh b/testsuite/synth/issue1302/testsuite.sh
new file mode 100755
index 000000000..ee9e3524a
--- /dev/null
+++ b/testsuite/synth/issue1302/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze testcase3
+grep -q rising_edge  syn_testcase3.vhdl
+
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3