From 060840d4176d7e5b775616e8a702bd751765c753 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 27 Jun 2022 08:24:50 +0200 Subject: synth/netlists-disp_verilog: adjust previous patch. For #2109 --- src/synth/netlists-disp_verilog.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 8eb76d332..b2461bf2f 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -1150,7 +1150,8 @@ package body Netlists.Disp_Verilog is and then Id in Edge_Module_Id and then not Need_Edge (Inst)) or else (not Flag_Null_Wires - or else Get_Width (Get_Output (Inst, 0)) = 0) + and then Get_Nbr_Outputs (Inst) = 1 + and then Get_Width (Get_Output (Inst, 0)) = 0) then -- Not displayed. null; -- cgit v1.2.3