From 01f485580d90cdea224e15aa3d583f5c987d2c77 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 24 Sep 2016 21:00:28 +0200
Subject: Add testcase for issue #148

---
 testsuite/gna/issue148/bug_sim.vhdl | 17 +++++++++++++++++
 testsuite/gna/issue148/testsuite.sh |  9 +++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 testsuite/gna/issue148/bug_sim.vhdl
 create mode 100755 testsuite/gna/issue148/testsuite.sh

diff --git a/testsuite/gna/issue148/bug_sim.vhdl b/testsuite/gna/issue148/bug_sim.vhdl
new file mode 100644
index 000000000..2a27adcc0
--- /dev/null
+++ b/testsuite/gna/issue148/bug_sim.vhdl
@@ -0,0 +1,17 @@
+entity bug is
+    port(data: out integer);
+end entity bug;
+
+architecture arc of bug is
+begin
+end architecture arc;
+
+entity bug_sim is
+end entity bug_sim;
+
+architecture sim of bug_sim is
+    signal data: natural;
+begin
+    u0: entity work.bug
+        port map(data => data);
+end architecture sim;
diff --git a/testsuite/gna/issue148/testsuite.sh b/testsuite/gna/issue148/testsuite.sh
new file mode 100755
index 000000000..baa136e35
--- /dev/null
+++ b/testsuite/gna/issue148/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze bug_sim.vhdl
+elab_failure bug_sim
+clean
+
+echo "Test successful"
-- 
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