| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: handle for-loop statements. | Tristan Gingold | 2019-07-01 | 2 | -1/+40 |
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| * | netlists disp_vhdl: rewrite uextend. | Tristan Gingold | 2019-07-01 | 1 | -5/+7 |
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| * | synth: handle more concat. | Tristan Gingold | 2019-06-30 | 1 | -0/+19 |
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| * | ghdlsimul: fix warning. | Tristan Gingold | 2019-06-30 | 1 | -1/+1 |
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| * | synth: add ule, fix gate number. | Tristan Gingold | 2019-06-30 | 3 | -30/+41 |
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| * | synth: handle more comparisons. | Tristan Gingold | 2019-06-30 | 1 | -11/+29 |
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| * | vhdl: recognize more predefined std_logic_unsigned functions. | Tristan Gingold | 2019-06-30 | 2 | -0/+24 |
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| * | synth: handle various enum ranges for case stmts. | Tristan Gingold | 2019-06-30 | 1 | -4/+24 |
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| * | synth: handle 2 states fsms. | Tristan Gingold | 2019-06-30 | 1 | -1/+5 |
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| * | netlists: add a comment. | Tristan Gingold | 2019-06-30 | 1 | -0/+11 |
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| * | synth: handle process statement. | Tristan Gingold | 2019-06-30 | 1 | -6/+43 |
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| * | synth: handle std_logic_unsigned."+" | Tristan Gingold | 2019-06-30 | 3 | -1/+17 |
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| * | synth: handle "=" from std_logic_unsigned. | Tristan Gingold | 2019-06-29 | 1 | -1/+2 |
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| * | vhdl: recognize std_logic_unsigned | Tristan Gingold | 2019-06-29 | 4 | -1/+155 |
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| * | ghdlcomp: fix warnings. | Tristan Gingold | 2019-06-29 | 1 | -4/+1 |
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| * | ghdl_jit: almost add ghdlsynth | Tristan Gingold | 2019-06-29 | 3 | -0/+2 |
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| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 16 | -23/+23 |
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| * | ghdldrv: refactoring - share more code, isolate ghdlsynth from ghdlsimul. | Tristan Gingold | 2019-06-29 | 6 | -123/+111 |
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| * | synth: disp_vhdl: merge literals. | Tristan Gingold | 2019-06-28 | 4 | -88/+154 |
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| * | synth: Move get_input_net to netlists.utils. | Tristan Gingold | 2019-06-28 | 6 | -8/+9 |
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| * | synth: fix disp_vhdl. Can now be analyzed. | Tristan Gingold | 2019-06-28 | 1 | -68/+159 |
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| * | synth: handle some functions from math_real. | Tristan Gingold | 2019-06-28 | 1 | -1/+43 |
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| * | vhdl: recognize some functions of math_real. | Tristan Gingold | 2019-06-28 | 5 | -3/+91 |
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| * | std_names: add names for math_real. | Tristan Gingold | 2019-06-28 | 2 | -1/+7 |
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| * | synth: disp_vhdl: handle mux2 | Tristan Gingold | 2019-06-28 | 2 | -3/+32 |
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| * | synth: add get_input_net helper. | Tristan Gingold | 2019-06-28 | 7 | -19/+32 |
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| * | synth: disp_vhdl: add disp_template. | Tristan Gingold | 2019-06-28 | 1 | -23/+46 |
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| * | synth: improve disp_vhdl. | Tristan Gingold | 2019-06-28 | 1 | -80/+232 |
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| * | synth: add syn_extract for dynamic slices. | Tristan Gingold | 2019-06-28 | 6 | -63/+273 |
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| * | synth: handle slice assignment. | Tristan Gingold | 2019-06-25 | 5 | -31/+71 |
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| * | Error_Msg_Option: do not raise exception. | Tristan Gingold | 2019-06-25 | 18 | -157/+177 |
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| * | libraries: add Get_Library_No_Create. | Tristan Gingold | 2019-06-24 | 2 | -10/+18 |
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| * | synth: add insert gate. | Tristan Gingold | 2019-06-24 | 6 | -16/+110 |
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| * | synth: handle discrete choice in case statements. | Tristan Gingold | 2019-06-23 | 2 | -6/+10 |
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| * | synth: handle more operators. | Tristan Gingold | 2019-06-23 | 2 | -12/+18 |
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| * | synth: remove unused Value_Logic. | Tristan Gingold | 2019-06-23 | 4 | -38/+5 |
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| * | synth: handle ult comparison. | Tristan Gingold | 2019-06-23 | 2 | -28/+39 |
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| * | vhdl: recognize more numeric_std predefined functions. | Tristan Gingold | 2019-06-23 | 2 | -0/+55 |
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| * | synth: handle more predefined functions. | Tristan Gingold | 2019-06-23 | 5 | -26/+115 |
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| * | synth-stmts: fix for unordered choices in case statement. | Tristan Gingold | 2019-06-23 | 1 | -5/+14 |
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| * | synth-stmts: handle constant if statements. | Tristan Gingold | 2019-06-23 | 1 | -2/+18 |
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| * | files_map: change the meaning of Get_Buffer_Length for | Tristan Gingold | 2019-06-20 | 3 | -2/+5 |
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| * | errorout-memory: avoid a crash after the limit is | Tristan Gingold | 2019-06-20 | 2 | -2/+5 |
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| * | vhdl-sem_names: do not crash on user attribute on | Tristan Gingold | 2019-06-20 | 1 | -1/+2 |
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| * | synth-expr: clarify error message. | Tristan Gingold | 2019-06-20 | 1 | -2/+7 |
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| * | files_map: add comments. | Tristan Gingold | 2019-06-20 | 2 | -2/+6 |
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| * | vhdl: recognize to_integer/to_signed/to_unsigned. | Tristan Gingold | 2019-06-20 | 4 | -1/+66 |
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| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 14 | -611/+1291 |
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| * | vhdl: decouple annotations from environments. | Tristan Gingold | 2019-06-19 | 8 | -204/+190 |
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| * | fix: move src/xtools to python/xtools (#846) | 1138-4EB | 2019-06-17 | 4 | -933/+4 |
| | | | | | | | * fix: move src/xtools to python/xtools * fix Makefiles affected by xtools and pnodes being moved | ||||
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index : iCE40/ghdl | |
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