iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth-decls: handle initial value for variables and	Tristan Gingold	2019-07-02	1	-5/+4
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*	netlists-disp_vhdl: handle xor.	Tristan Gingold	2019-07-02	1	-0/+2
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*	synth: fix Idff; fix 'edge and enable'.	Tristan Gingold	2019-07-02	2	-9/+6
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*	libghdlsynth: do not depend on ghdlsimul.	Tristan Gingold	2019-07-02	1	-3/+10
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*	ghdlsynth_gates.h: rebuild.	Tristan Gingold	2019-07-02	1	-29/+33
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*	ghdllocal: fix a typo in an error message.	Tristan Gingold	2019-07-02	1	-1/+1
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*	vhdl: adjust python pathes in Makefile.	Tristan Gingold	2019-07-02	1	-9/+11
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*	synth: destroy iterator after for-loop.	Tristan Gingold	2019-07-01	6	-10/+54
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*	synth: improve handling of dynamic slices, add a	Tristan Gingold	2019-07-01	1	-3/+30
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*	netlists-disp_vhdl: handle dyn_insert, fix mul.	Tristan Gingold	2019-07-01	1	-20/+36
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*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	7	-28/+130
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*	netlists-dump: write const in hexa.	Tristan Gingold	2019-07-01	1	-7/+9
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*	netlists-disp_vhdl: handle numbers in disp_template.	Tristan Gingold	2019-07-01	1	-14/+22
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*	netlists: fix pasto in builders.	Tristan Gingold	2019-07-01	1	-1/+1
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*	synth: add types_utils package.	Tristan Gingold	2019-07-01	3	-3/+31
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*	ghdlsynth: add option to select the output format.	Tristan Gingold	2019-07-01	1	-6/+16
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*	ghdldrv: add comments, analyze files for --synth/-e	Tristan Gingold	2019-07-01	3	-1/+7
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*	vhdl: improve error message.	Tristan Gingold	2019-07-01	1	-2/+1
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*	synth: handle for-loop statements.	Tristan Gingold	2019-07-01	2	-1/+40
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*	netlists disp_vhdl: rewrite uextend.	Tristan Gingold	2019-07-01	1	-5/+7
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*	synth: handle more concat.	Tristan Gingold	2019-06-30	1	-0/+19
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*	ghdlsimul: fix warning.	Tristan Gingold	2019-06-30	1	-1/+1
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*	synth: add ule, fix gate number.	Tristan Gingold	2019-06-30	3	-30/+41
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*	synth: handle more comparisons.	Tristan Gingold	2019-06-30	1	-11/+29
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*	vhdl: recognize more predefined std_logic_unsigned functions.	Tristan Gingold	2019-06-30	2	-0/+24
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*	synth: handle various enum ranges for case stmts.	Tristan Gingold	2019-06-30	1	-4/+24
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*	synth: handle 2 states fsms.	Tristan Gingold	2019-06-30	1	-1/+5
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*	netlists: add a comment.	Tristan Gingold	2019-06-30	1	-0/+11
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*	synth: handle process statement.	Tristan Gingold	2019-06-30	1	-6/+43
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*	synth: handle std_logic_unsigned."+"	Tristan Gingold	2019-06-30	3	-1/+17
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*	synth: handle "=" from std_logic_unsigned.	Tristan Gingold	2019-06-29	1	-1/+2
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*	vhdl: recognize std_logic_unsigned	Tristan Gingold	2019-06-29	4	-1/+155
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*	ghdlcomp: fix warnings.	Tristan Gingold	2019-06-29	1	-4/+1
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*	ghdl_jit: almost add ghdlsynth	Tristan Gingold	2019-06-29	3	-0/+2
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*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	16	-23/+23
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*	ghdldrv: refactoring - share more code, isolate ghdlsynth from ghdlsimul.	Tristan Gingold	2019-06-29	6	-123/+111
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*	synth: disp_vhdl: merge literals.	Tristan Gingold	2019-06-28	4	-88/+154
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*	synth: Move get_input_net to netlists.utils.	Tristan Gingold	2019-06-28	6	-8/+9
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*	synth: fix disp_vhdl. Can now be analyzed.	Tristan Gingold	2019-06-28	1	-68/+159
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*	synth: handle some functions from math_real.	Tristan Gingold	2019-06-28	1	-1/+43
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*	vhdl: recognize some functions of math_real.	Tristan Gingold	2019-06-28	5	-3/+91
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*	std_names: add names for math_real.	Tristan Gingold	2019-06-28	2	-1/+7
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*	synth: disp_vhdl: handle mux2	Tristan Gingold	2019-06-28	2	-3/+32
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*	synth: add get_input_net helper.	Tristan Gingold	2019-06-28	7	-19/+32
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*	synth: disp_vhdl: add disp_template.	Tristan Gingold	2019-06-28	1	-23/+46
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*	synth: improve disp_vhdl.	Tristan Gingold	2019-06-28	1	-80/+232
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*	synth: add syn_extract for dynamic slices.	Tristan Gingold	2019-06-28	6	-63/+273
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*	synth: handle slice assignment.	Tristan Gingold	2019-06-25	5	-31/+71
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*	Error_Msg_Option: do not raise exception.	Tristan Gingold	2019-06-25	18	-157/+177
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*	libraries: add Get_Library_No_Create.	Tristan Gingold	2019-06-24	2	-10/+18
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