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* synth: handle alias of alias. Fix #1945Tristan Gingold2022-01-121-2/+15
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* synth: refine handling of interface type. Fix #1944Tristan Gingold2022-01-102-8/+22
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* trans-chap2.adb: handle Kind_Component in Copy_Info. Fix #1943Tristan Gingold2022-01-091-1/+8
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* vhdl-sem_types: handle record in reparse_as_array_constraint. Fix #1934Tristan Gingold2022-01-091-0/+3
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* synth: ignore use clauses in finalization Fix #1942Tristan Gingold2022-01-051-0/+2
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* synth: handle package instantiation in declarations. Fix #1938Tristan Gingold2022-01-034-1/+12
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* vhdl-sem_decls: copy subtype indication also for files. Fix #1936Tristan Gingold2021-12-281-0/+3
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* dyn_maps: add Get_Index_Soft.Tristan Gingold2021-12-282-12/+50
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* synth: add assertionsTristan Gingold2021-12-191-0/+4
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* ghdldrv: fix crash due to double initializationTristan Gingold2021-12-192-2/+3
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* synth: handle interface type in generics. For #412Tristan Gingold2021-12-154-28/+49
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* mcode: generate and register .eh_frame on linux x86/64Tristan Gingold2021-12-1414-11/+179
| | | | This is needed to generate backtraces.
* ghdldrv: handle generic overrides on foreign unitsTristan Gingold2021-12-134-50/+75
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* vhdl-sem_expr.adb: avoid a crash after forced analysisTristan Gingold2021-12-131-1/+2
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* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
| | | | | | | This regressed in 86fd1ab3 ("synth: do full elaboration before synthesis") 1 Nov 2021
* synth: add --latches option to enable latches. Fix #938Tristan Gingold2021-12-063-1/+11
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* vhdl-sem.adb: fix incorrect check for conformance rulesTristan Gingold2021-12-031-1/+3
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* synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926Tristan Gingold2021-11-291-19/+11
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* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-282-4/+9
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* elab-vhdl_objtypes.adb: add an assertionTristan Gingold2021-11-281-0/+2
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* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
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* synth: adjustments for foreign_moduleTristan Gingold2021-11-282-3/+12
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* synth: add a hook to resolve foreign instantiation namesTristan Gingold2021-11-282-0/+8
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* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
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* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
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* vhdl-parse: improve error message for empty recordsTristan Gingold2021-11-281-29/+33
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* vhdl/translate: handle target aggregate with unbounded names. Fix #1914Tristan Gingold2021-11-244-22/+75
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* vhdl-sem_decls: avoid a crash on invalid alias name. Fix #1919Tristan Gingold2021-11-211-0/+10
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* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
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* synth: put direction into port descTristan Gingold2021-11-178-31/+30
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* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
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* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
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* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
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* synth: add ports attributesTristan Gingold2021-11-173-0/+120
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* vhdl-utils.adb: minor refactoringTristan Gingold2021-11-171-7/+3
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* grt: refactoring to fix build failure. For #1913Tristan Gingold2021-11-175-394/+443
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* Add commentsTristan Gingold2021-11-172-0/+4
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* vhdl-evaluation: use grt to compute value attribute for integers.Tristan Gingold2021-11-173-33/+97
| | | | For #1913
* grt/Makefile.inc: add a dependency for grt-cgnatrts.Tristan Gingold2021-11-161-2/+3
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* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
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* vhdl-evaluation: catch bad parameter for value attribute. Fix #1913Tristan Gingold2021-11-151-1/+7
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* vhdl-sem_expr: improve code generation for multi-dim aggregatesTristan Gingold2021-11-151-3/+3
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* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
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* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
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* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
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* std_names: add syn_black_boxTristan Gingold2021-11-122-1/+3
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* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
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* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
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* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-112-4/+20
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-0923-662/+730
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
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