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* synth: add ports attributesTristan Gingold2021-11-173-0/+120
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* vhdl-utils.adb: minor refactoringTristan Gingold2021-11-171-7/+3
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* grt: refactoring to fix build failure. For #1913Tristan Gingold2021-11-175-394/+443
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* Add commentsTristan Gingold2021-11-172-0/+4
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* vhdl-evaluation: use grt to compute value attribute for integers.Tristan Gingold2021-11-173-33/+97
| | | | For #1913
* grt/Makefile.inc: add a dependency for grt-cgnatrts.Tristan Gingold2021-11-161-2/+3
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* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
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* vhdl-evaluation: catch bad parameter for value attribute. Fix #1913Tristan Gingold2021-11-151-1/+7
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* vhdl-sem_expr: improve code generation for multi-dim aggregatesTristan Gingold2021-11-151-3/+3
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* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
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* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
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* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
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* std_names: add syn_black_boxTristan Gingold2021-11-122-1/+3
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* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
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* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
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* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-112-4/+20
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-0923-662/+730
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* lists: add a subtype for valid listsTristan Gingold2021-11-092-2/+4
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* ghdlcomp: exit with error status in case of error. For #1908Tristan Gingold2021-11-051-0/+4
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* vhdl-configuration: stop earlier in case of error. Fix #1908Tristan Gingold2021-11-051-17/+19
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* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-058-64/+143
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* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-049-362/+422
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* vhdl: add tok_inherit. Preliminary work for #1899Tristan Gingold2021-11-035-21/+27
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* trans-chap7: convert to base type for array-element operation. For #1898Tristan Gingold2021-11-031-3/+5
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* synth: Support alias declarations in vunittmeissner2021-11-026-8/+23
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* synth: do full elaboration before synthesisTristan Gingold2021-11-0161-2038/+5349
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* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-015-219/+256
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* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
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* vhdl-configuration.adb: avoid a crash in case of error. Fix #1897Tristan Gingold2021-10-181-2/+11
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* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
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* ortho/debug and ortho/oread: also increase identifier buffers. For #1894Tristan Gingold2021-10-182-2/+2
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* trans.adb: increased maximum identifier length. Fix #1894Tristan Gingold2021-10-161-1/+1
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* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
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* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-135-4/+12
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* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
| | | | And add comments
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
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* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
| | | | For ghdl/ghdl-yosys-plugin#159
* vhdl-scanner: improve error message. Fix #1883Tristan Gingold2021-10-061-1/+2
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* version.in: reformatting, simplify the Makefile ruleTristan Gingold2021-10-061-7/+7
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* elab-order command: add an option to display libraries. Fix #1736Tristan Gingold2021-10-041-4/+27
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* grt-change_generics: handle subtype for elements. Fix #1386Tristan Gingold2021-10-031-2/+8
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* vhdl: report unused types and subtypesTristan Gingold2021-10-012-1/+13
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* vhdl-formatters: fix bad reformatting on a simple range.Tristan Gingold2021-10-011-0/+1
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* vhdl: warns on unused component declarationsTristan Gingold2021-09-302-1/+5
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* grt-vcd.adb: add option --vcd-4states to dump a strict vcd file. Fix #1759Tristan Gingold2021-09-301-7/+17
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* grt-vcd: exclude arrays from dump. Fix #1881Tristan Gingold2021-09-291-59/+67
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* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
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* grt-change_generics: handle array subtypes. Fix #1876Tristan Gingold2021-09-241-6/+20
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* Add parsing of case? statement and simple test.Brian Padalino2021-09-248-79/+138
| | | | Also add the Matching flag to the Iir_Kind_Case_Statement.
* ghdldrv: use environment variable CC to set the default compiler. For #1629Tristan Gingold2021-09-231-3/+6
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