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* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-049-362/+422
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* vhdl: add tok_inherit. Preliminary work for #1899Tristan Gingold2021-11-035-21/+27
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* trans-chap7: convert to base type for array-element operation. For #1898Tristan Gingold2021-11-031-3/+5
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* synth: Support alias declarations in vunittmeissner2021-11-026-8/+23
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* synth: do full elaboration before synthesisTristan Gingold2021-11-0161-2038/+5349
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* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-015-219/+256
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* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
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* vhdl-configuration.adb: avoid a crash in case of error. Fix #1897Tristan Gingold2021-10-181-2/+11
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* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
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* ortho/debug and ortho/oread: also increase identifier buffers. For #1894Tristan Gingold2021-10-182-2/+2
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* trans.adb: increased maximum identifier length. Fix #1894Tristan Gingold2021-10-161-1/+1
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* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
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* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-135-4/+12
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* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
| | | | And add comments
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
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* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
| | | | For ghdl/ghdl-yosys-plugin#159
* vhdl-scanner: improve error message. Fix #1883Tristan Gingold2021-10-061-1/+2
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* version.in: reformatting, simplify the Makefile ruleTristan Gingold2021-10-061-7/+7
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* elab-order command: add an option to display libraries. Fix #1736Tristan Gingold2021-10-041-4/+27
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* grt-change_generics: handle subtype for elements. Fix #1386Tristan Gingold2021-10-031-2/+8
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* vhdl: report unused types and subtypesTristan Gingold2021-10-012-1/+13
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* vhdl-formatters: fix bad reformatting on a simple range.Tristan Gingold2021-10-011-0/+1
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* vhdl: warns on unused component declarationsTristan Gingold2021-09-302-1/+5
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* grt-vcd.adb: add option --vcd-4states to dump a strict vcd file. Fix #1759Tristan Gingold2021-09-301-7/+17
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* grt-vcd: exclude arrays from dump. Fix #1881Tristan Gingold2021-09-291-59/+67
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* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
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* grt-change_generics: handle array subtypes. Fix #1876Tristan Gingold2021-09-241-6/+20
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* Add parsing of case? statement and simple test.Brian Padalino2021-09-248-79/+138
| | | | Also add the Matching flag to the Iir_Kind_Case_Statement.
* ghdldrv: use environment variable CC to set the default compiler. For #1629Tristan Gingold2021-09-231-3/+6
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* vhdl-ieee-vital_timing.adb: handle vhdl 2008. Fix #1875Tristan Gingold2021-09-231-3/+15
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* vhdl-evaluation.adb: Minor style fixesTristan Gingold2021-09-231-60/+61
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* vhdl-sem_assocs.adb: add commentsTristan Gingold2021-09-231-10/+41
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* Add explicit ?>= and ?> functions for translation.Brian Padalino2021-09-226-4/+30
| | | | | | Instead of swapping L/R arguments to try to create ?>= and ?>, create a function for each which performs the not operation of ?< and ?<= as defined by the LRM.
* Implement Matching Operators (#1872)Brian Padalino2021-09-221-8/+148
| | | Implement the matching operators ?<, ?<=, ?>, ?>=, ?/=.
* vhdl-evaluation.adb: handle iir_kind_aggregate in build_constant. Fix #543Tristan Gingold2021-09-181-0/+11
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* vhdl-parse.adb: minor reformattingTristan Gingold2021-09-181-1/+2
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* trans-chap8: fix iteration on an enumeration type with only one literal.Tristan Gingold2021-09-181-3/+9
| | | | Fix #1514
* trans-chap8.adb: refactoring and clean-up. For #1514Tristan Gingold2021-09-182-46/+12
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* vhdl-sem_names(sem_parenthesis_name): minor refactoringTristan Gingold2021-09-181-13/+9
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* vhdl-sem_names(sem_parenthesis_name): handle indexing of delayed attribute.Tristan Gingold2021-09-181-2/+6
| | | | Fix #1515
* configure and Makefile: link ghdl with grt-cstdioTristan Gingold2021-09-173-3/+4
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* vhdl-evaluation.adb: fix warningTristan Gingold2021-09-171-3/+0
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* vhdl-evaluation: implement to_string for real with format. Fix #874Tristan Gingold2021-09-171-23/+69
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* vhdl-utils: minor renaming for homogeneityTristan Gingold2021-09-162-2/+2
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* trans-chap4: handle unbounded aggregate initial value to unbounded signal.Tristan Gingold2021-09-161-1/+30
| | | | Fix #1857
* Fixed some typos (#1868)Patrick Lehmann2021-09-1611-22/+22
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* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
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* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
| | | | For #1866
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
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* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-153-18/+25
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