iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	synth: fix conversion of net to constant for physical values. Fix #1148	Tristan Gingold	2020-03-02	2	-6/+11
*	vhdl-prints: disable code to display anonymous signal.	Tristan Gingold	2020-03-02	1	-2/+10
*	Remove --ieee=mentor and build of mentor libraries.	Tristan Gingold	2020-03-02	2	-9/+11
*	Fix regressions after previous commit.	Tristan Gingold	2020-03-01	1	-0/+5
*	vhdl: a function call is not an object. Fix #1138.	Tristan Gingold	2020-03-01	3	-15/+33
*	vhdl-parse: avoid error cascade for 'subtype before 08.	Tristan Gingold	2020-03-01	1	-1/+0
*	synth: top entity name is not anymore hashed by default.	Tristan Gingold	2020-03-01	6	-83/+138
*	synth-insts: add comments, minor refactoring.	Tristan Gingold	2020-02-29	3	-9/+6
*	synth: handle more physical operators. Fix #1146	Tristan Gingold	2020-02-29	4	-21/+80
*	synth-static_oper: handle enum inequality.	Tristan Gingold	2020-02-29	1	-0/+3
*	synth-decls: fix handling of record subtypes.	Tristan Gingold	2020-02-29	1	-1/+14
*	vhdl-parse: improve error messages and recovery.	Tristan Gingold	2020-02-27	1	-8/+46
*	synth: handle file_close.	Tristan Gingold	2020-02-27	3	-10/+31
*	synth-static_oper: handle to_stdlogicvector_bv	Tristan Gingold	2020-02-27	1	-1/+20
*	Update copyright years before the release.	Tristan Gingold	2020-02-26	1	-1/+1
*	vhdl: handle CR+LF for readline in grt. Fix #1145	Tristan Gingold	2020-02-25	2	-18/+62
*	netlists: rework memories to fix port orders, add a loop.	Tristan Gingold	2020-02-23	7	-46/+85
*	netlists-memories: also reduce muxes for extract.	Tristan Gingold	2020-02-21	1	-7/+35
*	synth-decls: handle alias declaration without subtype indication.	Tristan Gingold	2020-02-21	1	-2/+7
*	netlists-memories: factorize code.	Tristan Gingold	2020-02-20	1	-235/+191
*	netlists-inference: preliminary work to support else in synch code.	Tristan Gingold	2020-02-20	1	-71/+153
*	netlists: add midff	Tristan Gingold	2020-02-20	3	-0/+47
*	disable backtrace on android (#1142)	umarcor	2020-02-19	1	-1/+1
*	vhdl: recognize conversion functions from std_logic_1164	Tristan Gingold	2020-02-18	5	-12/+70
*	synth: rework static predefined function calls.	Tristan Gingold	2020-02-18	3	-152/+224
*	synth: handle file_open.	Tristan Gingold	2020-02-18	3	-0/+48
*	synth-environment: handle unassigned outputs.	Tristan Gingold	2020-02-18	1	-6/+8
*	netlists-cleanup: refactoring.	Tristan Gingold	2020-02-18	1	-12/+17
*	synth-insts: handle slices in individual associations.	Tristan Gingold	2020-02-18	1	-0/+21
*	vhdl-sem_scopes: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	1	-1/+2
*	vhdl-configuration: ignore configuration for top_level_entity.	Tristan Gingold	2020-02-18	1	-4/+4
*	synth-expr: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	2	-6/+10
*	vhdl-sem_assocs: recurse for individual associations.	Tristan Gingold	2020-02-17	1	-23/+64
*	synth: allow constant condition for if-generate statement.	Tristan Gingold	2020-02-17	1	-0/+1
*	synth: add mdff.	Tristan Gingold	2020-02-17	4	-12/+88
*	netlists-inference: remove useless code.	Tristan Gingold	2020-02-16	1	-10/+0
*	synthesis: rework memory inference.	Tristan Gingold	2020-02-16	3	-32/+101
*	synth: handle component with ports in different order.	Tristan Gingold	2020-02-13	3	-45/+46
*	vhdl-parse: improve recovery for incorrect end identifier.	Tristan Gingold	2020-02-13	1	-8/+27
*	files_maps-editor: fix incorrect assertion.	Tristan Gingold	2020-02-13	1	-1/+1
*	vhdl-sem_expr: avoid a crash on incorrect qualified expr.	Tristan Gingold	2020-02-13	1	-0/+6
*	synth-static_oper: handle more division operands. Fix #1134	Tristan Gingold	2020-02-12	1	-1/+2
*	synth: handle null vector for vec-vec concat. Fix #1133	Tristan Gingold	2020-02-11	2	-6/+12
*	synth-oper: handle add for (natural, unsigned). Fix #1132	Tristan Gingold	2020-02-11	1	-0/+15
*	netlists-memories: handle split memories. Fix #1127	Tristan Gingold	2020-02-11	1	-8/+18
*	translate: refine condition. Fix #1125	Tristan Gingold	2020-02-11	1	-1/+1
*	synth-static_oper: handle xor.	Tristan Gingold	2020-02-10	1	-0/+11
*	synth-expr: implement value and val attributes. Fix #1130	Tristan Gingold	2020-02-10	1	-1/+39
*	grt: split grt-errors, disp current process.	Tristan Gingold	2020-02-10	18	-104/+183
*	synth: remove remaining clock edge gates after memories.	Tristan Gingold	2020-02-10	2	-0/+26