iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	netlists: add assume gate.	Tristan Gingold	2019-07-04	5	-3/+29
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*	libghdlsynth: decode options.	Tristan Gingold	2019-07-04	3	-76/+104
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*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	17	-57/+57
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*	parse: improve error message for incorrect use of '!'.	Tristan Gingold	2019-07-04	1	-0/+4
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*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	18	-109/+261
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*	Move pnodes.py.py to xtools directory.	Tristan Gingold	2019-07-04	1	-1/+1
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*	synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.	Tristan Gingold	2019-07-04	5	-17/+30
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*	synth: emit an error for non-constant bounds.	Tristan Gingold	2019-07-04	1	-0/+4
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*	synth: ignore non object aliases.	Tristan Gingold	2019-07-03	1	-0/+2
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*	vhdl: translate anonymous_signal_declaration.	Tristan Gingold	2019-07-03	4	-9/+8
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*	vhdl: avoid a crash on label parenthesis.	Tristan Gingold	2019-07-03	1	-0/+1
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*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	18	-186/+384
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*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	7	-1/+50
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*	synth-expr: remove useless code.	Tristan Gingold	2019-07-02	1	-5/+1
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*	synth-decls: handle initial value for variables and	Tristan Gingold	2019-07-02	1	-5/+4
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*	netlists-disp_vhdl: handle xor.	Tristan Gingold	2019-07-02	1	-0/+2
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*	synth: fix Idff; fix 'edge and enable'.	Tristan Gingold	2019-07-02	2	-9/+6
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*	libghdlsynth: do not depend on ghdlsimul.	Tristan Gingold	2019-07-02	1	-3/+10
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*	ghdlsynth_gates.h: rebuild.	Tristan Gingold	2019-07-02	1	-29/+33
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*	ghdllocal: fix a typo in an error message.	Tristan Gingold	2019-07-02	1	-1/+1
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*	vhdl: adjust python pathes in Makefile.	Tristan Gingold	2019-07-02	1	-9/+11
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*	synth: destroy iterator after for-loop.	Tristan Gingold	2019-07-01	6	-10/+54
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*	synth: improve handling of dynamic slices, add a	Tristan Gingold	2019-07-01	1	-3/+30
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*	netlists-disp_vhdl: handle dyn_insert, fix mul.	Tristan Gingold	2019-07-01	1	-20/+36
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*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	7	-28/+130
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*	netlists-dump: write const in hexa.	Tristan Gingold	2019-07-01	1	-7/+9
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*	netlists-disp_vhdl: handle numbers in disp_template.	Tristan Gingold	2019-07-01	1	-14/+22
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*	netlists: fix pasto in builders.	Tristan Gingold	2019-07-01	1	-1/+1
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*	synth: add types_utils package.	Tristan Gingold	2019-07-01	3	-3/+31
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*	ghdlsynth: add option to select the output format.	Tristan Gingold	2019-07-01	1	-6/+16
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*	ghdldrv: add comments, analyze files for --synth/-e	Tristan Gingold	2019-07-01	3	-1/+7
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*	vhdl: improve error message.	Tristan Gingold	2019-07-01	1	-2/+1
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*	synth: handle for-loop statements.	Tristan Gingold	2019-07-01	2	-1/+40
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*	netlists disp_vhdl: rewrite uextend.	Tristan Gingold	2019-07-01	1	-5/+7
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*	synth: handle more concat.	Tristan Gingold	2019-06-30	1	-0/+19
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*	ghdlsimul: fix warning.	Tristan Gingold	2019-06-30	1	-1/+1
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*	synth: add ule, fix gate number.	Tristan Gingold	2019-06-30	3	-30/+41
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*	synth: handle more comparisons.	Tristan Gingold	2019-06-30	1	-11/+29
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*	vhdl: recognize more predefined std_logic_unsigned functions.	Tristan Gingold	2019-06-30	2	-0/+24
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*	synth: handle various enum ranges for case stmts.	Tristan Gingold	2019-06-30	1	-4/+24
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*	synth: handle 2 states fsms.	Tristan Gingold	2019-06-30	1	-1/+5
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*	netlists: add a comment.	Tristan Gingold	2019-06-30	1	-0/+11
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*	synth: handle process statement.	Tristan Gingold	2019-06-30	1	-6/+43
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*	synth: handle std_logic_unsigned."+"	Tristan Gingold	2019-06-30	3	-1/+17
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*	synth: handle "=" from std_logic_unsigned.	Tristan Gingold	2019-06-29	1	-1/+2
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*	vhdl: recognize std_logic_unsigned	Tristan Gingold	2019-06-29	4	-1/+155
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*	ghdlcomp: fix warnings.	Tristan Gingold	2019-06-29	1	-4/+1
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*	ghdl_jit: almost add ghdlsynth	Tristan Gingold	2019-06-29	3	-0/+2
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*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	16	-23/+23
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*	ghdldrv: refactoring - share more code, isolate ghdlsynth from ghdlsimul.	Tristan Gingold	2019-06-29	6	-123/+111
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