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* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-055-48/+55
* binary_file-coff: fix symbols writeTristan Gingold2022-04-051-29/+58
* ortho/mcode: fix win64 stack alignmentTristan Gingold2022-04-041-1/+1
* ortho/mcode: generate unwind info on win64 (WIP)Tristan Gingold2022-04-043-2/+100
* ortho/mcode: handle image relative relocation (for Win64)Tristan Gingold2022-04-043-4/+29
* ortho/mcode: handle x86-64 coff image dump (WIP)Tristan Gingold2022-04-043-24/+31
* synth: handle individual assoc of unbounded interface. Fix #2023Tristan Gingold2022-04-042-1/+4
* synth: handle shared variable without default value.Tristan Gingold2022-04-042-1/+4
* mcode: improve support of Win64 (prolog)Tristan Gingold2022-04-013-29/+41
* grt-readline.ads: use types from grt-typesTristan Gingold2022-03-301-16/+5
* mcode: improve support of Win64 (allocate stack for home registers)Tristan Gingold2022-03-303-6/+22
* Add chkstk-x64 for windows x64Tristan Gingold2022-03-303-2/+70
* translate: adjust null access check: add an explicit check.Tristan Gingold2022-03-266-31/+66
* trans-chap6: add an explicit memory access during fat access deferenceTristan Gingold2022-03-251-0/+10
* ghdldrv: extract ghdllib from ghdlsynthTristan Gingold2022-03-226-63/+115
* grt: extract grt-vhdl_types from grt-typesTristan Gingold2022-03-2232-139/+195
* synth-vhdl_expr: minor refactoring - add commentsTristan Gingold2022-03-201-16/+34
* synth-vhdl_expr(value2logvec): fix vlen handling. Fix #2013Tristan Gingold2022-03-201-7/+13
* synth-vhdl_context: adjust mask. Fix #2011Tristan Gingold2022-03-181-1/+1
* vhdl-19: analyze return identifierTristan Gingold2022-03-161-0/+18
* Fix include-dir paths returned by cmdline _again_Daniel Gröber2022-03-141-1/+2
* vhdl: check access type restrictions also on completion. Fix #2006Tristan Gingold2022-03-133-25/+32
* Fix hardcoded values in gcc backend's default_pathsDaniel Gröber2022-03-131-44/+0
* netlists-disp_verilog: fix disp_const_bitTristan Gingold2022-03-121-2/+2
* vhdl: check association restrictions for operators. Fix #1999Tristan Gingold2022-03-113-170/+181
* synth: check matching bounds for concatenationTristan Gingold2022-03-112-2/+4
* mk: Introduce configure options for inc/libdirsuffixDaniel Gröber2022-03-116-28/+31
* Fix --libghdl-include-dir ghdl/ suffixDaniel Gröber2022-03-111-1/+3
* synth: add debug_btTristan Gingold2022-03-084-0/+56
* synth: handle concatenation of unbounded types. Fix #1993Tristan Gingold2022-03-089-111/+64
* grt-signals.adb: Suppress overflow check before manual check. Fix #1994Tristan Gingold2022-03-051-6/+11
* vhdl-sem_names: fix a crash with select of element attribute. Fix #1992Tristan Gingold2022-03-041-1/+2
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-045-210/+284
* synth-vhdl_oper: implement <= for arrays. Fix #1991Tristan Gingold2022-03-022-7/+19
* elab-vhdl_expr.adb(exec_name_subtype): handle indexed names. Fix #1986Tristan Gingold2022-03-021-0/+8
* vhdl-sem_decls: allow out/inout parameters to impure function in VHDL-2019Xiretza2022-03-011-3/+15
* vhdl-sem_types: allow methods to return file and protected types in -2019Xiretza2022-03-011-1/+3
* vhdl-sem_types: allow file and protected type access types in -2019Xiretza2022-03-011-7/+12
* Add --std=19Xiretza2022-02-287-5/+16
* Prepare for release 2.0.0Tristan Gingold2022-02-281-1/+1
* ortho/mcode: relax assertion (and fix debug code). Fix #1980Tristan Gingold2022-02-262-2/+6
* trans-chap6.adb: fix minor typing issueTristan Gingold2022-02-261-2/+11
* vhdl-sem_psl.adb: don't crash on overload in HDL expr. Fix #1979Tristan Gingold2022-02-241-2/+12
* synth: fix handling of record constraints in subtype. Fix #1961Tristan Gingold2022-02-222-5/+28
* elab-vhdl_values.adb: fix a typo. Fix #1968Tristan Gingold2022-02-181-2/+2
* synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977Tristan Gingold2022-02-171-27/+30
* synth: properly propagate bound errors. Fix #1972Tristan Gingold2022-02-174-16/+38
* synth-vhdl_oper: handle bit condition operator. Fix #1971Tristan Gingold2022-02-161-1/+2
* synth-vhdl_aggr: fix mismatch. Fix #1962Tristan Gingold2022-02-051-1/+6
* synth: fix handling of std_logic_unsigned."-" for negative numbers.Tristan Gingold2022-01-181-8/+12
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