aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl/vhdl-prints.adb
Commit message (Collapse)AuthorAgeFilesLines
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+2
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-3/+15
|
* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-261-0/+4
|
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-25/+0
|
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-2/+3
|
* psl: prefix of goto/non-consecutive repetition is a bool. Fix #1708Tristan Gingold2021-04-031-8/+15
|
* Add base support for the attribue element in vhdl 08Anselmo952021-04-031-0/+2
|
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+20
| | | | | | | | | | | | | | | * vhdl: parse PSL onehot/onehot0 builtin calls. For #662 * update pyGHDL bindings * Synthesis of PSL built-in onehot/onehot0 function. * testsuite/synth: add tests of PSL built-in functions onehot()/onehot0() for #662 * doc: add info about PSL built-in functions onehot()/onehot0() for #662 * synth: refactor synthesis of onehot/onehot0 functions Co-authored-by: eine <eine@users.noreply.github.com>
* update license headersumarcor2021-01-141-11/+9
|
* vhdl-formatters: add realignmentTristan Gingold2021-01-111-1/+12
|
* vhdl: rework formatter engine, add 'ghdl fmt' commandTristan Gingold2021-01-091-2/+1
|
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-16/+20
|
* vhdl-prints: avoid assertion on empty hbox for simple loopTristan Gingold2021-01-041-7/+16
|
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+31
| | | | For #1416
* Synthesis of PSL built-in fell() function.tmeissner2020-06-071-0/+17
|
* Synthesis of PSL built-in rose() function.tmeissner2020-06-061-0/+17
|
* Synthesis of PSL stable() function.tmeissner2020-06-061-0/+17
|
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-1/+25
|
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-1/+1
| | | | Global renaming.
* vhdl-prints: handle evaluated expression for qualified_expression.Tristan Gingold2020-04-181-16/+19
|
* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
|
* vhdl-prints: disable code to display anonymous signal.Tristan Gingold2020-03-021-2/+10
|
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+2
|
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-8/+7
|
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-40/+89
|
* ams-vhdl: handle record nature end name.Tristan Gingold2019-12-301-0/+2
|
* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-1/+36
|
* ams-vhdl: print subnature declarations.Tristan Gingold2019-12-301-1/+16
|
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-127/+405
|
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+2
|
* vhdl-prints: subtype indication is optional in object alias.Tristan Gingold2019-12-261-3/+2
|
* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
|
* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
|
* psl: add active state.Tristan Gingold2019-10-211-0/+7
|
* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
|
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
|
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-3/+4
|
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-201-1/+1
|
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
|
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
|
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+13
|
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-141-6/+6
|
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-1/+5
|
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+2
| | | | For #877
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-5/+4
|
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl-prints: improve output for ports/generics.Tristan Gingold2019-07-221-5/+27
|
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-6/+6
|
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-1/+18
|
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+13
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-22 23:58:41 +0000