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* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-0/+4
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-4/+4
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* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-1/+11
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* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+3
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* synth: handle verification units.Tristan Gingold2019-08-201-0/+1
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-67/+134
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* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-141-0/+9
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* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-141-37/+33
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* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-101-2/+22
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+3
| | | | For #877
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-061-0/+3
| | | | For #877
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
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* parse: improve error message for incorrect use of '!'.Tristan Gingold2019-07-041-0/+4
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-3/+25
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* vhdl-parse: improve error message in case of unexpectedTristan Gingold2019-06-131-0/+12
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* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-6/+14
| | | | Add Literal_Length and set it in the parser.
* vhdl: move Current_Text from vhdl-utils to vhdl-parse.Tristan Gingold2019-05-251-0/+20
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* vhdl: update AMS parsing.Tristan Gingold2019-05-241-1/+15
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* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-0/+2
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* vhdl-parse: minor changes for disp_vhdl.Tristan Gingold2019-05-241-0/+5
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* vhdl: add hook on free_node, automatically freeTristan Gingold2019-05-221-3/+0
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* vhdl-parse: strenghten.Tristan Gingold2019-05-151-9/+13
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* errorout: add messages group instead of continuation.Tristan Gingold2019-05-121-24/+27
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* vhdl-parse: improve error messages. Fix #818Tristan Gingold2019-05-111-0/+14
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* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-3/+5
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* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
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* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-3/+3
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
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* vhdl-nodes_utils: renaming.Tristan Gingold2019-05-071-43/+42
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* vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.Tristan Gingold2019-05-061-46/+54
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
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* vhdl: move xrefs to vhdl child package.Tristan Gingold2019-05-061-1/+1
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* vhdl: move elocations* packages to vhdl children.Tristan Gingold2019-05-051-1/+1
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* vhdl: move parse package as vhdl child.Tristan Gingold2019-05-041-0/+9871
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