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* vhdl: recognize rotate functions.Tristan Gingold2019-09-221-0/+5
* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+22
* vhdl-nodes: add a comment.Tristan Gingold2019-09-121-1/+1
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-111-0/+5
* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-071-0/+7
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-3/+4
* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-021-0/+4
* vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-301-0/+7
* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-301-0/+2
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-201-0/+4
* synth: handle verification units.Tristan Gingold2019-08-201-1/+13
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-23/+30
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-6/+58
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-151-0/+21
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-0/+4
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-7/+0
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-15/+16
* vhdl-nodes: gather PSL nodes, regenerate nodes_meta.Tristan Gingold2019-08-071-30/+4
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-5/+12
* synth: add support for memories.Tristan Gingold2019-07-291-0/+2
* vhdl: linearize analyze and evaluation of concat operators.Tristan Gingold2019-07-261-0/+1
* vhdl+synth: recognize /= to std_logic_unsigned.Tristan Gingold2019-07-251-1/+5
* vhdl: recognize resize function.Tristan Gingold2019-07-241-0/+5
* synth: add > and >= operators (#870)Pepijn de Vos2019-07-161-0/+8
* vhdl-nodes: add commentsTristan Gingold2019-07-111-0/+16
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-5/+5
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-1/+32
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+26
* vhdl: recognize more predefined std_logic_unsigned functions.Tristan Gingold2019-06-301-0/+8
* synth: handle std_logic_unsigned."+"Tristan Gingold2019-06-301-0/+6
* vhdl: recognize std_logic_unsignedTristan Gingold2019-06-291-1/+6
* vhdl: recognize some functions of math_real.Tristan Gingold2019-06-281-1/+5
* vhdl: recognize more numeric_std predefined functions.Tristan Gingold2019-06-231-0/+35
* vhdl: recognize to_integer/to_signed/to_unsigned.Tristan Gingold2019-06-201-0/+7
* vhdl-nodes: add Node_List and Node_Flist aliases.Tristan Gingold2019-06-121-0/+2
* synth: added support for numeric_std unary negationChristos Gentsos2019-06-061-1/+5
* synth: handle numeric_std subtraction (addition was already there)Christos Gentsos2019-06-061-0/+7
* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-1/+3
* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-16/+30
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-10/+3
* vhdl: update AMS parsing.Tristan Gingold2019-05-241-0/+4
* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-0/+2
* vhdl-nodes: make subtype_Definition like the others.Tristan Gingold2019-05-231-0/+4
* vhdl: add hook on free_node, automatically freeTristan Gingold2019-05-221-0/+4
* vhdl-nodes: fix minor typo.Tristan Gingold2019-05-111-1/+1
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-4/+10
* Make lists a generic package, add vhdl-lists.Tristan Gingold2019-05-091-1/+1
* flists is now a generic package, add vhdl-flistsTristan Gingold2019-05-091-1/+1
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-0/+7549
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