| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: parse PSL inherit spec. For #1899 | Tristan Gingold | 2021-11-04 | 1 | -0/+1 |
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| * | vhdl: remove iir_kind_anonymous_signal_declaration (now unused) | Tristan Gingold | 2021-08-24 | 1 | -1/+0 |
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| * | vhdl: introduce iir_kind_association_element_by_name | Tristan Gingold | 2021-08-06 | 1 | -0/+1 |
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| * | vhdl: add Iir_Kind_Foreign_Module | Tristan Gingold | 2021-04-05 | 1 | -0/+1 |
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| * | Add support for PSL onehot/onehot0 functions (#1633) | T. Meissner | 2021-02-09 | 1 | -0/+2 |
| | | | | | | | | | | | | | | | | * vhdl: parse PSL onehot/onehot0 builtin calls. For #662 * update pyGHDL bindings * Synthesis of PSL built-in onehot/onehot0 function. * testsuite/synth: add tests of PSL built-in functions onehot()/onehot0() for #662 * doc: add info about PSL built-in functions onehot()/onehot0() for #662 * synth: refactor synthesis of onehot/onehot0 functions Co-authored-by: eine <eine@users.noreply.github.com> | ||||
| * | Update copyright headers for vhdl-elocations* | Tristan Gingold | 2021-02-04 | 1 | -1/+1 |
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| * | update license headers | umarcor | 2021-01-14 | 1 | -11/+9 |
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| * | vhdl: parse subprogram instantiations. For #1470 | Tristan Gingold | 2020-09-24 | 1 | -0/+2 |
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| * | vhdl: parse and analyze force/release signal assignment statements. | Tristan Gingold | 2020-08-01 | 1 | -0/+2 |
| | | | | | For #1416 | ||||
| * | vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662 | Tristan Gingold | 2020-06-02 | 1 | -0/+4 |
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| * | ams-vhdl: add support for 'delayed for quantity. | Tristan Gingold | 2019-12-31 | 1 | -0/+1 |
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| * | ams-vhdl: handle zoh, ltf and ztf attributes. | Tristan Gingold | 2019-12-31 | 1 | -0/+3 |
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| * | ams-vhdl: add simultaneous null statement. | Tristan Gingold | 2019-12-30 | 1 | -0/+2 |
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| * | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 1 | -2/+43 |
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| * | vhdl: parse verification unit (WIP). | Tristan Gingold | 2019-08-17 | 1 | -0/+1 |
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| * | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 1 | -2/+5 |
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| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 |
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| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -0/+1 |
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| * | vhdl: add anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+1 |
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| * | vhdl: add hook on free_node, automatically free | Tristan Gingold | 2019-05-22 | 1 | -1/+21 |
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| * | vhdl: move nodes to vhdl.nodes_priv. | Tristan Gingold | 2019-05-05 | 1 | -4/+4 |
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| * | vhdl: move elocations* packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -0/+710 |
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index : iCE40/ghdl | |
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