aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl/vhdl-canon.adb
Commit message (Collapse)AuthorAgeFilesLines
* vhdl-canon: remove signal parameters for all-sensitized processes.Tristan Gingold2023-02-081-1/+43
| | | | Fix #2344
* vhdl: reduce use of is_anonymous_type_definitionTristan Gingold2023-02-031-10/+12
|
* vhdl/trans: support suspend statesTristan Gingold2023-01-281-0/+5
|
* vhdl-sem_inst: handle suspend_stateTristan Gingold2023-01-041-4/+7
|
* simul: handle force/release signal assignmentsTristan Gingold2023-01-031-2/+4
|
* vhdl-canon: handle unaffectedTristan Gingold2022-12-261-0/+1
|
* vhdl-sem_inst: add instantiate_component_declaration.Tristan Gingold2022-12-231-4/+8
| | | | For #2264
* vhdl-canon: avoid a crash on optionnal condition. Fix #2212Tristan Gingold2022-10-101-1/+1
|
* vhdl-canon: extract guard for signal assignment sensitivityTristan Gingold2022-09-291-1/+15
|
* vhdl-canon: handle conditional variable assignment. Fix #2138Tristan Gingold2022-07-251-1/+16
|
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-1/+1
| | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
* vhdl-cannon: add Canon_Extract_Sensitivity_Break_StatementTristan Gingold2022-07-161-1/+12
|
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-071-0/+3
| | | | Fix crash in translation (tentatively)
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-4/+184
|
* vhdl-canon: refactoring.Tristan Gingold2022-05-161-31/+66
| | | | Export procedures to extract sensitivity from concurrent statements
* vhdl-sem_names(sem_check_all_sensitized): only consider interface signalTristan Gingold2022-04-151-0/+2
|
* synth: handle type declarations in vunit. Fix #2034Tristan Gingold2022-04-131-0/+1
|
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+2
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-051-1/+2
|
* synth: Support alias declarations in vunittmeissner2021-11-021-1/+3
|
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-0/+2
|
* Fixed some typos (#1868)Patrick Lehmann2021-09-161-2/+2
|
* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-121-12/+23
|
* vhdl,psl: abort is now identical to async_abort. For #1654Tristan Gingold2021-09-021-3/+2
|
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-0/+11
|
* vhdl-canon: detect PSL assertion that cannot fail. For #1832Tristan Gingold2021-08-291-2/+12
|
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-60/+0
|
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-5/+5
|
* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-0/+1
|
* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-151-0/+2
|
* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-151-0/+1
|
* vhdl and libraries: add support for binding to a foreign moduleTristan Gingold2021-04-051-6/+19
|
* vhdl-canon.adb: handle individual assoc in extract sensitivity. Fix #1684Tristan Gingold2021-03-131-0/+2
|
* vhdl-canon.adb: add a missing check on generic associations. Fix #1655Tristan Gingold2021-02-201-0/+3
|
* update license headersumarcor2021-01-141-11/+9
|
* vhdl-canon: canon generic associations for subprogram instantiations.Tristan Gingold2020-09-281-1/+6
|
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-6/+9
|
* vhdl-canon: minor cleanup.Tristan Gingold2020-08-081-57/+0
|
* vhdl: renaming in vhdl-canon.Tristan Gingold2020-08-081-182/+195
|
* vhdl: check missing association to generics. Fix #1379Tristan Gingold2020-06-261-0/+9
|
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-158/+190
|
* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-7/+12
|
* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
|
* synth: simplify support of inertial associations.Tristan Gingold2020-01-091-1/+1
|
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-4/+23
|
* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-0/+11
|
* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-291-1/+2
| | | | Also fix use and canon for it.
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-2/+148
|
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-1/+3
|
* vhdl-canon: handle simple signal assignment in vunits.Tristan Gingold2019-10-251-273/+272
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-24 08:04:21 +0000