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* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-151-0/+2
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* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-151-0/+1
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* vhdl and libraries: add support for binding to a foreign moduleTristan Gingold2021-04-051-6/+19
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* vhdl-canon.adb: handle individual assoc in extract sensitivity. Fix #1684Tristan Gingold2021-03-131-0/+2
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* vhdl-canon.adb: add a missing check on generic associations. Fix #1655Tristan Gingold2021-02-201-0/+3
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* update license headersumarcor2021-01-141-11/+9
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* vhdl-canon: canon generic associations for subprogram instantiations.Tristan Gingold2020-09-281-1/+6
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* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-6/+9
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* vhdl-canon: minor cleanup.Tristan Gingold2020-08-081-57/+0
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* vhdl: renaming in vhdl-canon.Tristan Gingold2020-08-081-182/+195
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* vhdl: check missing association to generics. Fix #1379Tristan Gingold2020-06-261-0/+9
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-158/+190
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* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-7/+12
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* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
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* synth: simplify support of inertial associations.Tristan Gingold2020-01-091-1/+1
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-4/+23
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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-0/+11
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* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-291-1/+2
| | | | Also fix use and canon for it.
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-2/+148
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* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-1/+3
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* vhdl-canon: handle simple signal assignment in vunits.Tristan Gingold2019-10-251-273/+272
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* vhdl-canon: extract canon_concurrent_label.Tristan Gingold2019-10-251-20/+25
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* vhdl-canon: handle some declarations in vunits.Tristan Gingold2019-10-231-2/+18
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* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-151-0/+7
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* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-0/+4
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-1/+1
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* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+2
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* synth: handle verification units.Tristan Gingold2019-08-201-31/+57
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-0/+2
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-27/+37
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* vhdl: cleanup in clear_instantiation_configuration.Tristan Gingold2019-07-131-2/+2
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* vhdl: minor reformating.Tristan Gingold2019-07-111-3/+3
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-14/+26
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* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-13/+61
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* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-2/+2
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* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
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* Extract psl-errors from errorout.Tristan Gingold2019-05-101-1/+2
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
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* vhdl: remove too strict assertion in canon. Fix #816Tristan Gingold2019-05-071-11/+3
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* vhdl-nodes_utils: renaming.Tristan Gingold2019-05-071-13/+13
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* vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.Tristan Gingold2019-05-061-11/+12
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
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* vhdl: move sem* packages to vhdl children.Tristan Gingold2019-05-051-3/+3
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* vhdl: move canon to a vhdl child package.Tristan Gingold2019-05-051-0/+3290
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