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path: root/src/vhdl/translate/trans-rtis.adb
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-1/+1
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
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* vhdl: move configuration package as a vhdl child.Tristan Gingold2019-05-051-2/+2
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* trans-rtis: take into account instances in the count of packages.Tristan Gingold2018-11-241-4/+15
| | | | rtis: check number of packages.
* trans-rtis: fix uninitialized variable.Tristan Gingold2018-10-241-3/+8
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* Rework translation of unbounded and complex types.Tristan Gingold2018-10-211-122/+127
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* translate: remove other use of Nam_Buffer.Tristan Gingold2018-01-201-13/+7
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* Rework array/record type mode to improve support of constrained records.Tristan Gingold2018-01-111-15/+19
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* Use flist for enumerations.Tristan Gingold2017-11-071-2/+2
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* Use Flist for records.Tristan Gingold2017-11-071-3/+2
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* Use Flist for array indexes.Tristan Gingold2017-11-061-2/+2
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* unbounded records: add rti support (WIP)Tristan Gingold2017-02-211-55/+76
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* vhdl08: allow PSL default clock declaration in block declarative parts.Tristan Gingold2017-01-131-0/+5
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* WIP for unconstrained records.Tristan Gingold2017-01-131-1/+1
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* translate: WIP - refactoring for unbounded records.Tristan Gingold2017-01-021-1/+1
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* translate: WIP for unbounded records.Tristan Gingold2017-01-021-1/+1
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* translate: refactoring for ortho_info_type.Tristan Gingold2016-12-301-19/+19
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* vhdl08: support top-level macro-expanded package instantiation declarations.Tristan Gingold2016-12-051-4/+7
| | | | Fixes #199
* WIP for nested instantiation of macro-expansed packages.Tristan Gingold2016-11-121-17/+23
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* Add signal_attribute_declaration to hold implicit atribute signals.Tristan Gingold2016-10-081-20/+29
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* Rework range_expression and incomplete type for instantiation.Tristan Gingold2016-09-301-3/+2
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* vhdl08: strengthten nested packages.Tristan Gingold2016-09-121-1/+8
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* vhdl08: preliminary work to support nested package bodies.Tristan Gingold2016-09-041-0/+11
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* vhdl08: handle very simple nested packages.Tristan Gingold2016-09-031-58/+76
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* vhdl08: add support of case-generate statementTristan Gingold2016-07-071-16/+49
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* PSL: add clocked SERE, make endpoints visible from VHDL.Tristan Gingold2016-03-221-3/+11
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* PSL: add counters, generate rti and add --psl-reportTristan Gingold2016-03-181-30/+51
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* ortho: rename start/finish_const_value to start/finish_init_value.Tristan Gingold2016-02-211-44/+44
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* Pass signal values to interfaces. 'sigptr' optimization.Tristan Gingold2015-12-181-1/+1
| | | | Improve simulation speed by about 20%.
* trans-rtis: fix uninitialized field (that could result in a crash).Tristan Gingold2015-09-151-10/+8
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* Replace fat accesses by bounds accessesTristan Gingold2015-08-291-19/+23
| | | | | translate: separate info for signals from object. Improve some error messages.
* Handle vhdl08 if generate statementsTristan Gingold2015-01-071-186/+302
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* Rework for vhdl08 generate: change rtis.Tristan Gingold2015-01-041-82/+193
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* Initial rework for vhdl 2008 generate statements.Tristan Gingold2015-01-031-37/+75
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* Rename name_table.name_buffer and name_length to avoid clash.Tristan Gingold2014-12-311-6/+6
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* Use same node for implicit and explicit subprogram declarations.Tristan Gingold2014-12-151-6/+2
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* iirs: reduce size of signal_declaration.Tristan Gingold2014-12-141-3/+9
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* rtis: add source location for blocks and object. Use them in fst dumper.Tristan Gingold2014-12-131-27/+97
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* Split translation into child packages.Tristan Gingold2014-11-091-0/+2559
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