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* netlists-dump: indent output.Tristan Gingold2019-11-053-13/+17
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* netlists-memories: adjust message.Tristan Gingold2019-11-051-1/+1
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* netlists: enable expansion.Tristan Gingold2019-11-041-1/+1
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* synth-oper: handle constant not.Tristan Gingold2019-11-041-3/+8
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* synth-expr: allow constants in discrete rangeTristan Gingold2019-11-041-0/+2
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* synth-expr: handle vhdl 2008 aggregates (partially).Tristan Gingold2019-11-042-48/+125
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* synth-value: export get_bound_length.Tristan Gingold2019-11-041-0/+3
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* netlists-expands: expand rol.Tristan Gingold2019-11-031-0/+30
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* synth-oper: use build2_uresizeTristan Gingold2019-11-031-16/+2
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* netlists-utils: add clog2Tristan Gingold2019-11-032-0/+8
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* netlists-builders: add build2_uresize.Tristan Gingold2019-11-032-0/+31
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* synth: fix multiport read memories (for issue #1000)Tristan Gingold2019-11-031-1/+3
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* synth: cap max in synth_slice_suffixTristan Gingold2019-11-031-1/+8
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* netlists-expands: rewrite generate_muxes.Tristan Gingold2019-11-031-24/+102
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* netlists-expands: use a safe walk.Tristan Gingold2019-11-031-1/+3
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* synth: add support for inout variable interfaces.Tristan Gingold2019-11-012-3/+4
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* synth-values: handle value_const for is_equal.Tristan Gingold2019-11-011-0/+5
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* synth: handle nested if generate statements.Tristan Gingold2019-11-012-21/+29
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* netlits: fix memidx order.Tristan Gingold2019-11-012-39/+52
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* netlists-dump: improve output.Tristan Gingold2019-11-011-10/+11
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* netlists-expands: expand dyn_insertTristan Gingold2019-11-012-42/+174
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* ghdlsynth_gates.h: regenerate.Tristan Gingold2019-10-311-0/+4
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* synth: handle attributes in vunit.Tristan Gingold2019-10-301-1/+86
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* netlists: add formal input gates.Tristan Gingold2019-10-303-0/+44
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* netlists-expands: handle 2d arrays.Tristan Gingold2019-10-281-83/+72
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* synth: adjust computation of max for dyn_extract.Tristan Gingold2019-10-283-8/+10
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* netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.Tristan Gingold2019-10-281-1/+3
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* synth-expr (synth_slice_suffix): compute max value for slices.Tristan Gingold2019-10-271-1/+4
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* netlists-expand: truncate address if needed.Tristan Gingold2019-10-271-0/+10
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* netlists: add code to expand dyn_extract gates (WIP).Tristan Gingold2019-10-275-1/+259
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* netlists: change Loc parameter of synth_case.Tristan Gingold2019-10-275-6/+21
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* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-277-38/+48
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* netlists-butils: extract synth_case from synth.stmts.Tristan Gingold2019-10-263-149/+206
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* synth: handle concurrent signal assignment in vunits.Tristan Gingold2019-10-251-83/+89
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* synth: add support for declarations in vunits.Tristan Gingold2019-10-232-4/+27
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* netlists-dump: dump input net width.Tristan Gingold2019-10-231-0/+2
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* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-211-0/+1
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* synth: generate cover for assertion precedent.Tristan Gingold2019-10-215-84/+103
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* nelists-memories: reject memories with reset.Tristan Gingold2019-10-211-1/+4
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* synth-stmts: set location of muxes on case statements.Tristan Gingold2019-10-211-6/+13
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* synth: fixes for value_const.Tristan Gingold2019-10-202-0/+11
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* netlists-memories: fixes in ROM.Tristan Gingold2019-10-201-48/+51
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* netlists-disp_vhdl: display memory initialization value.Tristan Gingold2019-10-201-2/+46
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* synth: add value_const.Tristan Gingold2019-10-207-9/+69
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* netlists-memories: preliminary work to handle ROM.Tristan Gingold2019-10-201-111/+194
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* synth: add more locations.Tristan Gingold2019-10-202-0/+2
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* netlists-dump: also dump instances location.Tristan Gingold2019-10-201-6/+34
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* synth: use note messages for memories (instead of warnings).Tristan Gingold2019-10-194-28/+34
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* ghdlsynth.h: add functions.Tristan Gingold2019-10-191-0/+4
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* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-181-0/+5
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