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* synth-disp_vhdl: extend vector conversions (for any range). For #1460Tristan Gingold2020-09-201-2/+20
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* synth-expr: refine is_positive for wires. For #1460Tristan Gingold2020-09-201-2/+6
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* synth: handle static resize. For #1460Tristan Gingold2020-09-203-0/+36
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* synth: handle find_leftmost/find_rigthmost. For #1460Tristan Gingold2020-09-191-0/+77
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* vhdl: recognize reduce operations from numeric_std.Tristan Gingold2020-09-141-6/+18
| | | | Handle them in synthesis.
* synth: improve support of interface package. For #1460Tristan Gingold2020-09-133-66/+105
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* netlists-cleanup: do not remove user sub modules. Fix #1454Tristan Gingold2020-09-051-3/+7
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* synth-static_oper: fix crash on exponential. Fix #1442Tristan Gingold2020-08-261-1/+1
| | | | | Allow negative value for the right operand of ** for floating point values.
* synth: handle evaluated string literals without constraints.Tristan Gingold2020-08-261-2/+24
| | | | Fix #1430
* synth: improve diagnostic for multiple assignment. Fix #1428Tristan Gingold2020-08-265-19/+191
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* synth-stmts: convert the waveform to the target subtype.Tristan Gingold2020-08-251-7/+13
| | | | fix ghdl/ghdl-yosys-plugin#129
* synth-oper: handle operators of std_logic_unsigned.Tristan Gingold2020-08-071-65/+99
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* synth-oper: handle more std_logic_arith operators.Tristan Gingold2020-08-071-226/+180
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* netlists: preliminary support of memory of depth one.Tristan Gingold2020-08-061-2/+0
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* synth: handle an operation from std_logic_unsigned. For #1426Tristan Gingold2020-08-061-1/+2
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* synth-oper: handle more operations for std_logic_arith. For #1426Tristan Gingold2020-08-062-142/+339
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* synth-oper: propagate errors from unsupported operations.Tristan Gingold2020-08-061-2/+7
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* synth-disp_vhdl: minor output indentation fix.Tristan Gingold2020-08-061-1/+1
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* synth-oper: handle < for enums.Tristan Gingold2020-08-061-0/+2
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* synth: push extract on mux2 for inference. For #1421Tristan Gingold2020-08-063-17/+52
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* synth-oper: handle std_logic_arith."=" for unsigned. Fix #1424Tristan Gingold2020-08-041-0/+1
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* synth: fix handling of static index in indexed names. For #1421Tristan Gingold2020-08-032-2/+3
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* synth: add --no-assert-cover option. Fix #1414Tristan Gingold2020-07-312-6/+13
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* synth: do not consider all ieee packages as predefined.Tristan Gingold2020-07-301-7/+24
| | | | | | | In particular, the vhdl 2008 fixed point packages are considered as regular packages. Fix #1417
* synth: add support for static numeric_std division.Tristan Gingold2020-07-304-0/+188
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* synth-stmts: improve support of instantiated subprograms. Fix #1408Tristan Gingold2020-07-271-3/+3
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* synth-expr: add minimal support for 'instance_name. For #1408Tristan Gingold2020-07-271-0/+14
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* synth: generalize static condition for if statement. Fix #1407Tristan Gingold2020-07-261-4/+4
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* synth-debugger: update code.Tristan Gingold2020-07-261-17/+15
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* synth: add -g option to enable debugger on some errors.Tristan Gingold2020-07-261-1/+1
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* synth-aggr: handle strings in aggregates. Fix #1406Tristan Gingold2020-07-251-0/+25
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* netlists-inference: do not infere a memory in case of reset.Tristan Gingold2020-07-251-0/+1
| | | | Fix ghdl/ghdl-yosys-plugin#128
* synth: fix handling of multi-dim ROM. Fix #1390Tristan Gingold2020-07-243-24/+26
| | | | Document index order for memidx.
* netlists-memories: minor style fix.Tristan Gingold2020-07-221-2/+2
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* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-0/+1
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* synth: disp_vhdl: const_x may not have a location.Tristan Gingold2020-07-211-0/+1
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* synth-oper: handle sub uns/log.Tristan Gingold2020-07-191-0/+1
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* synth-static_oper: factorize code.Tristan Gingold2020-07-181-18/+9
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* synth-decls: avoid elaboration crash after global signals. For #1387Tristan Gingold2020-07-181-1/+3
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* netlists-disp_vhdl: display inout ports as inout.Tristan Gingold2020-07-021-2/+8
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* synth-insts: set location on ports. For #1387Tristan Gingold2020-07-021-0/+2
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* synth-environment: allow multiple assignments from instance portsTristan Gingold2020-07-021-17/+16
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* synth: do not support signals declared in a package.Tristan Gingold2020-07-021-0/+5
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* vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641Tristan Gingold2020-06-301-2/+2
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* synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-5/+6
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* synth: handle to_x01. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-6/+10
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* synth: avoid crash on invalid range. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-192-9/+15
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* synth-oper: handle add_uns_int_slv. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-181-1/+2
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* ghdlsynth: add --no-formal and help.Tristan Gingold2020-06-162-0/+29
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-152-1/+4
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