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synth
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Age
Files
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*
synth: display instances in reverse order.
Tristan Gingold
2019-07-10
2
-10
/
+41
*
synth: handle instantiation (WIP)
Tristan Gingold
2019-07-10
11
-48
/
+587
*
synthesis: add Node instead of Iir.
Tristan Gingold
2019-07-08
1
-10
/
+10
*
synth-environement: add comments.
Tristan Gingold
2019-07-08
2
-3
/
+5
*
synth: handle simple user function calls.
Tristan Gingold
2019-07-06
6
-18
/
+89
*
synth: support top-level generics.
Tristan Gingold
2019-07-06
2
-0
/
+23
*
ghdlsynth.h: follow convention, add comments.
Tristan Gingold
2019-07-04
1
-13
/
+16
*
vhdl-annotations: partial revert of previous patch for
Tristan Gingold
2019-07-04
1
-1
/
+2
*
synth: use future states for PSL restrict directive.
Tristan Gingold
2019-07-04
1
-5
/
+8
*
synth: handle some "/=".
Tristan Gingold
2019-07-04
1
-0
/
+3
*
libghdlsynth: catch all exceptions.
Tristan Gingold
2019-07-04
1
-0
/
+3
*
synth: handle PSL restrict directive (WIP).
Tristan Gingold
2019-07-04
2
-1
/
+111
*
synth: add concat_array function.
Tristan Gingold
2019-07-04
2
-36
/
+52
*
netlists-disp_vhdl: display initial value of idff.
Tristan Gingold
2019-07-04
1
-19
/
+32
*
netlists: export new_internal_name.
Tristan Gingold
2019-07-04
1
-4
/
+10
*
netlists: allow to build idff without a connected D.
Tristan Gingold
2019-07-04
2
-3
/
+6
*
netlists: add reduce_or/reduce_and gates.
Tristan Gingold
2019-07-04
4
-0
/
+36
*
netlists: add assume gate.
Tristan Gingold
2019-07-04
5
-3
/
+29
*
libghdlsynth: decode options.
Tristan Gingold
2019-07-04
1
-1
/
+8
*
vhdl: parse and analyze restrict directive.
Tristan Gingold
2019-07-04
1
-0
/
+2
*
synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.
Tristan Gingold
2019-07-04
4
-15
/
+28
*
synth: emit an error for non-constant bounds.
Tristan Gingold
2019-07-04
1
-0
/
+4
*
synth: ignore non object aliases.
Tristan Gingold
2019-07-03
1
-0
/
+2
*
synth: handle concurrent assertions.
Tristan Gingold
2019-07-02
6
-0
/
+48
*
synth-expr: remove useless code.
Tristan Gingold
2019-07-02
1
-5
/
+1
*
synth-decls: handle initial value for variables and
Tristan Gingold
2019-07-02
1
-5
/
+4
*
netlists-disp_vhdl: handle xor.
Tristan Gingold
2019-07-02
1
-0
/
+2
*
synth: fix Idff; fix 'edge and enable'.
Tristan Gingold
2019-07-02
2
-9
/
+6
*
libghdlsynth: do not depend on ghdlsimul.
Tristan Gingold
2019-07-02
1
-3
/
+10
*
ghdlsynth_gates.h: rebuild.
Tristan Gingold
2019-07-02
1
-29
/
+33
*
synth: destroy iterator after for-loop.
Tristan Gingold
2019-07-01
6
-10
/
+54
*
synth: improve handling of dynamic slices, add a
Tristan Gingold
2019-07-01
1
-3
/
+30
*
netlists-disp_vhdl: handle dyn_insert, fix mul.
Tristan Gingold
2019-07-01
1
-20
/
+36
*
synth: add dyn_insert module.
Tristan Gingold
2019-07-01
7
-28
/
+130
*
netlists-dump: write const in hexa.
Tristan Gingold
2019-07-01
1
-7
/
+9
*
netlists-disp_vhdl: handle numbers in disp_template.
Tristan Gingold
2019-07-01
1
-14
/
+22
*
netlists: fix pasto in builders.
Tristan Gingold
2019-07-01
1
-1
/
+1
*
synth: add types_utils package.
Tristan Gingold
2019-07-01
3
-3
/
+31
*
synth: handle for-loop statements.
Tristan Gingold
2019-07-01
2
-1
/
+40
*
netlists disp_vhdl: rewrite uextend.
Tristan Gingold
2019-07-01
1
-5
/
+7
*
synth: handle more concat.
Tristan Gingold
2019-06-30
1
-0
/
+19
*
synth: add ule, fix gate number.
Tristan Gingold
2019-06-30
3
-30
/
+41
*
synth: handle more comparisons.
Tristan Gingold
2019-06-30
1
-11
/
+29
*
synth: handle various enum ranges for case stmts.
Tristan Gingold
2019-06-30
1
-4
/
+24
*
synth: handle 2 states fsms.
Tristan Gingold
2019-06-30
1
-1
/
+5
*
netlists: add a comment.
Tristan Gingold
2019-06-30
1
-0
/
+11
*
synth: handle process statement.
Tristan Gingold
2019-06-30
1
-6
/
+43
*
synth: handle std_logic_unsigned."+"
Tristan Gingold
2019-06-30
1
-1
/
+2
*
synth: handle "=" from std_logic_unsigned.
Tristan Gingold
2019-06-29
1
-1
/
+2
*
vhdl: move annotations from simul to vhdl.
Tristan Gingold
2019-06-29
6
-6
/
+6
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