iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	vhdl-nodes: move maximum/minimum out of predefined operator range	Tristan Gingold	2022-05-30	1	-19/+19
*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	1	-15/+208
*	synth-vhdl_eval: handle resolution_limit	Tristan Gingold	2022-05-29	1	-0/+3
*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	1	-0/+30
*	synth-vhdl_eval: handle element-element concatenation	Tristan Gingold	2022-05-24	1	-0/+18
*	synth-vhdl_oper: add an hook for rising_edge	Tristan Gingold	2022-05-23	1	-4/+4
*	synth: use same elements for unbounded arrays and vectors	Tristan Gingold	2022-05-22	1	-3/+3
*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	1	-4/+4
*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-4/+5
*	synth-vhdl_eval: handle all comparisons for enums	Tristan Gingold	2022-04-29	1	-33/+29
*	synth-vhdl_eval: handle abs	Tristan Gingold	2022-04-27	1	-0/+2
*	synth: renaming (synth-static_oper -> synth-vhdl_eval)	Tristan Gingold	2022-04-27	1	-0/+1060