iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth-stmts: fix for unordered choices in case statement.	Tristan Gingold	2019-06-23	1	-5/+14
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*	synth-stmts: handle constant if statements.	Tristan Gingold	2019-06-23	1	-2/+18
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*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-45/+35
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*	synth-stmts: handle enumeration type in case, renaming.	Tristan Gingold	2019-06-13	1	-63/+72
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*	synth: handle conditional generate process.	Tristan Gingold	2019-06-11	1	-1/+45
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*	synth: support conditional signal assignments.	Tristan Gingold	2019-06-08	1	-6/+38
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*	synth: add comments and refactoring.	Tristan Gingold	2019-06-07	1	-1/+1
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*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-1/+1
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*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-1/+1
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*	vhdl: move evaluation to vhdl child.	Tristan Gingold	2019-05-05	1	-2/+2
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*	vhdl: move ieee packages to vhdl children.	Tristan Gingold	2019-05-05	1	-11/+11
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*	vhdl: move sem* packages to vhdl children.	Tristan Gingold	2019-05-05	1	-2/+2
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*	synth: ignore component instantiations (TODO).	Tristan Gingold	2019-04-16	1	-0/+4
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*	move algos to grt.	Tristan Gingold	2019-03-20	1	-2/+3
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*	fix gnat8 errors for libghdlsynth targets	Stefan Biereigel	2019-03-13	1	-1/+0
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*	evaluation: rename Get_Info to Get_Str_Info (reduce overloading).	Tristan Gingold	2017-12-08	1	-2/+1
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*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-9/+9
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*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+826