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path: root/src/synth/synth-stmts.adb
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* synth: move synth_user_function_call to synth-stmts.Tristan Gingold2019-09-111-1/+60
* synth: handle alias (WIP, read only).Tristan Gingold2019-09-111-8/+29
* synth: handle partial assignments in case statements.Tristan Gingold2019-09-071-22/+59
* synth: handle large width in get_net.Tristan Gingold2019-09-041-1/+3
* synth: handle conditional variable assignment.Tristan Gingold2019-09-021-0/+34
* synth: fix type elaboration of interfaces.Tristan Gingold2019-08-301-2/+0
* synth: ignore report statement.Tristan Gingold2019-08-301-0/+2
* synth: add support for record types.Tristan Gingold2019-08-291-62/+132
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-271-0/+2
* synth: rework partial assignmentsTristan Gingold2019-08-271-24/+24
* synth: set name to assert/assume gates.Tristan Gingold2019-08-201-4/+15
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+2
* synth: set location on assume/assert gates.Tristan Gingold2019-08-201-4/+13
* synth: handle verification units.Tristan Gingold2019-08-201-2/+19
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-131-4/+20
* synth: extract edge for PSL clocks.Tristan Gingold2019-08-131-27/+34
* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-131-4/+53
* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
* synth: handle subtype conversions.Tristan Gingold2019-08-051-24/+45
* synth: preliminary support of integer literals.Tristan Gingold2019-08-021-6/+2
* synth: rework indexed names.Tristan Gingold2019-07-301-34/+36
* synth: add support for memories.Tristan Gingold2019-07-291-3/+5
* synth: remove extract_bound (trivial).Tristan Gingold2019-07-281-1/+1
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-281-41/+34
* synth: preliminary support of integer subtypes.Tristan Gingold2019-07-261-1/+3
* synth: array inequality, integer in choices.Tristan Gingold2019-07-251-0/+4
* synth: save and display locations for instances.Tristan Gingold2019-07-251-1/+4
* synth: fix bad ordering in case statement.Tristan Gingold2019-07-241-2/+3
* synth: fix slice/indexed assignment that partially override previous assign.Tristan Gingold2019-07-231-5/+8
* synth: rework names.Tristan Gingold2019-07-221-1/+6
* synth: add support for concurrent selected signal assignment.Tristan Gingold2019-07-201-2/+138
* synth: initial support for for-generate statement.Tristan Gingold2019-07-201-29/+84
* synth: finalize concurrent assignments (WIP).Tristan Gingold2019-07-191-4/+12
* synth: make more types private.Tristan Gingold2019-07-171-1/+1
* synth: make type Wire_Id_Record private.Tristan Gingold2019-07-171-4/+4
* synth: renaming of Assign to Seq_Assign.Tristan Gingold2019-07-171-5/+5
* synth: handle instantiation within generate statement.Tristan Gingold2019-07-151-0/+2
* synth: handle choices by range in aggregates.Tristan Gingold2019-07-151-7/+11
* synth: use correct instance to synth default expressions of assocs.Tristan Gingold2019-07-151-10/+13
* synth: save and restore instance_pool for processes.Tristan Gingold2019-07-151-2/+4
* synth: handle black boxes.Tristan Gingold2019-07-131-1/+13
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-7/+6
* synth: handle simple user function calls.Tristan Gingold2019-07-061-3/+21
* synth: use future states for PSL restrict directive.Tristan Gingold2019-07-041-5/+8
* synth: handle PSL restrict directive (WIP).Tristan Gingold2019-07-041-0/+109
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-0/+2
* synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.Tristan Gingold2019-07-041-1/+2
* synth: handle concurrent assertions.Tristan Gingold2019-07-021-0/+18
* synth: destroy iterator after for-loop.Tristan Gingold2019-07-011-2/+10
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