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* synth: initial support of access types.Tristan Gingold2019-11-171-0/+2
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* synth: add support for file declarations.Tristan Gingold2019-11-131-0/+1
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* synth: add support for declarations in vunits.Tristan Gingold2019-10-231-0/+3
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* synth: handle package bodies.Tristan Gingold2019-10-071-0/+2
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* synth: preliminary support for user packages.Tristan Gingold2019-10-071-0/+3
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* synth: finalize declarations and free wires.Tristan Gingold2019-09-271-0/+4
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* synth: rework type for expression.Tristan Gingold2019-09-251-0/+4
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* synth: initialize subprogram variables.Tristan Gingold2019-09-131-3/+3
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* synth: destroy iterator after for-loop.Tristan Gingold2019-07-011-0/+7
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* synth: get rid of execution and elaboration.Tristan Gingold2019-06-191-0/+4
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* synth: handle enumerated types.Tristan Gingold2019-06-121-2/+2
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* synth: add comments and refactoring.Tristan Gingold2019-06-071-1/+1
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* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-1/+1
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* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+28