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* synth: renaming to instance_attributes.Tristan Gingold2021-11-171-1/+1
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* netlists-disp_vhdl: do not display edge net when not needed. Fix #1703Tristan Gingold2021-03-291-1/+0
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* update license headersumarcor2021-02-051-5/+3
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* netlists-inference: handle multiple dff with the same clock. Fix #1563Tristan Gingold2021-01-011-0/+4
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* netlists: complete support of attributes. For #1318Tristan Gingold2020-05-231-0/+3
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* netlits: Use Remove_Instance instead of Free_Instance.Tristan Gingold2020-05-181-4/+0
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* netlists: infere tri gate.Tristan Gingold2020-04-221-0/+4
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* netlists: add new helpers for yosys plugin.Tristan Gingold2020-03-311-1/+3
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* synth: add helper to support inout ports in yosys plugin. For #1166Tristan Gingold2020-03-291-0/+5
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* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-0/+4
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* netlists-memories: allow intermediate signals to detect sync read.Tristan Gingold2020-01-121-0/+4
| | | | Fix #1079
* synth-environment: also optimize mux merge for sub-nets.Tristan Gingold2019-12-311-0/+5
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* synth: handle wire assigned to a static value. Fix #1058Tristan Gingold2019-12-291-1/+5
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* synth: add Get_Input_Instance.Tristan Gingold2019-12-141-0/+5
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* dyn_tables: move Table_Initial generic to argument ofTristan Gingold2019-11-111-2/+6
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* synth: move net_table to netlists-utils.Tristan Gingold2019-11-111-0/+10
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* synth: do more constant propagation (on build2Tristan Gingold2019-11-051-0/+6
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* netlists-utils: add clog2Tristan Gingold2019-11-031-0/+2
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* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-271-1/+0
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* synth: rewrite cleanup pass.Tristan Gingold2019-10-101-7/+0
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* synth: fold addition on constant nets.Tristan Gingold2019-09-171-0/+1
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* synth: minor refactoring about const gates.Tristan Gingold2019-09-151-1/+1
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* synth: rework partial assignmentsTristan Gingold2019-08-271-0/+7
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* add port width utility function for yosys (#876)Pepijn de Vos2019-07-211-0/+3
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* synth: disp_vhdl: merge literals.Tristan Gingold2019-06-281-0/+3
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* synth: Move get_input_net to netlists.utils.Tristan Gingold2019-06-281-0/+2
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* synth: defer gates removal after at end of entity synthesis.Tristan Gingold2017-02-151-0/+6
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* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+44