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synth
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netlists-utils.adb
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Author
Age
Files
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*
netlists-disp_vhdl: do not display edge net when not needed. Fix #1703
Tristan Gingold
2021-03-29
1
-18
/
+1
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*
update license headers
umarcor
2021-02-05
1
-5
/
+3
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*
netlists-inference: handle multiple dff with the same clock. Fix #1563
Tristan Gingold
2021-01-01
1
-0
/
+13
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*
netlists: complete support of attributes. For #1318
Tristan Gingold
2020-05-23
1
-0
/
+14
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*
netlits: Use Remove_Instance instead of Free_Instance.
Tristan Gingold
2020-05-18
1
-37
/
+0
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*
netlists-builders: add Build_Pmux.
Tristan Gingold
2020-05-09
1
-1
/
+2
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*
netlists: infere tri gate.
Tristan Gingold
2020-04-22
1
-0
/
+14
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*
netlists: add new helpers for yosys plugin.
Tristan Gingold
2020-03-31
1
-0
/
+10
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*
synth: add helper to support inout ports in yosys plugin. For #1166
Tristan Gingold
2020-03-29
1
-0
/
+5
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*
netlists: get_net_uns64: handle id_const_sb32.
Tristan Gingold
2020-01-12
1
-0
/
+11
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*
netlists-utils: consider 0 bit net as static.
Tristan Gingold
2020-01-12
1
-0
/
+6
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*
netlists-utils: factorize code (same_net).
Tristan Gingold
2020-01-12
1
-15
/
+24
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*
netlists-memories: allow intermediate signals to detect sync read.
Tristan Gingold
2020-01-12
1
-0
/
+12
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Fix #1079
*
synth-environment: also optimize mux merge for sub-nets.
Tristan Gingold
2019-12-31
1
-0
/
+28
|
*
synth: handle wire assigned to a static value. Fix #1058
Tristan Gingold
2019-12-29
1
-0
/
+20
|
*
synth: add Get_Input_Instance.
Tristan Gingold
2019-12-14
1
-0
/
+6
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*
synth: do more constant propagation (on build2
Tristan Gingold
2019-11-05
1
-1
/
+28
|
*
netlists-utils: add clog2
Tristan Gingold
2019-11-03
1
-0
/
+6
|
*
synth: rewrite cleanup pass.
Tristan Gingold
2019-10-10
1
-59
/
+0
|
*
netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.
Tristan Gingold
2019-10-02
1
-0
/
+3
|
*
synth: fold addition on constant nets.
Tristan Gingold
2019-09-17
1
-0
/
+5
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*
synth: minor refactoring about const gates.
Tristan Gingold
2019-09-15
1
-3
/
+9
|
*
synth: add support for memories.
Tristan Gingold
2019-07-29
1
-1
/
+6
|
*
add port width utility function for yosys (#876)
Pepijn de Vos
2019-07-21
1
-0
/
+10
|
*
synth: add concatn gate
Tristan Gingold
2019-07-19
1
-9
/
+12
|
*
synth: disp_vhdl: merge literals.
Tristan Gingold
2019-06-28
1
-0
/
+15
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*
synth: Move get_input_net to netlists.utils.
Tristan Gingold
2019-06-28
1
-0
/
+5
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*
synth: defer gates removal after at end of entity synthesis.
Tristan Gingold
2017-02-15
1
-0
/
+59
|
*
Add netlist generation infrastructure.
Tristan Gingold
2017-01-31
1
-0
/
+126