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* synth: minor renaming in netlists-memoriesTristan Gingold2021-06-301-7/+8
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* update license headersumarcor2021-02-051-5/+3
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* synth: improve support of true dual port rams. For #1069Tristan Gingold2020-05-311-2/+3
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* netlists: rework clock handling in memories.Tristan Gingold2020-05-291-1/+2
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* synthesis: rework memory inference.Tristan Gingold2020-02-161-1/+1
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* synth: rework (again) memory inference.Tristan Gingold2020-02-101-0/+7
| | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
* netlists-memories: generate mem_rd_sync gates.Tristan Gingold2019-12-051-1/+0
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* netlists-memories: rework.Tristan Gingold2019-12-051-0/+1
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* netlists: add code to expand dyn_extract gates (WIP).Tristan Gingold2019-10-271-0/+4
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* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-171-0/+26