iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	synth: Add support for PSL cover directive (#930)	T. Meissner	2019-09-19	1	-0/+4
*	synth: minor refactoring about const gates.	Tristan Gingold	2019-09-15	1	-36/+22
*	synth: add const_x gate.	Tristan Gingold	2019-09-11	1	-1/+5
*	synth: introduce slice type.	Tristan Gingold	2019-09-11	1	-0/+4
*	synth: add const_sb32, add smul/umul.	Tristan Gingold	2019-09-07	1	-1/+1
*	synth: handle const_bit in disp_constant_inline.	Tristan Gingold	2019-09-04	1	-0/+4
*	synth: remove insert gate.	Tristan Gingold	2019-08-31	1	-22/+0
*	netlists-disp_vhdl: do not used literals for prefixes.	Tristan Gingold	2019-08-27	1	-12/+53
*	synth: set name to assert/assume gates.	Tristan Gingold	2019-08-20	1	-2/+8
*	netlist: fix minor pasto.	Tristan Gingold	2019-08-20	1	-1/+1
*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	1	-0/+13
*	synth: handle signed conversions in disp_vhdl.	Tristan Gingold	2019-08-05	1	-2/+6
*	synth: handle signed integer comparisons (#878)	Pepijn de Vos	2019-08-01	1	-0/+12
*	synth: adjust output for dyn_insert, add dpram2 test.	Tristan Gingold	2019-07-30	1	-2/+2
*	synth: fixes for indexed names.	Tristan Gingold	2019-07-30	1	-1/+1
*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-6/+58
*	synth: save and display locations for instances.	Tristan Gingold	2019-07-25	1	-0/+20
*	synth: fix incorrect slice in disp_vhdl for Insert.	Tristan Gingold	2019-07-25	1	-6/+1
*	synth: use original entity to display netlist.	Tristan Gingold	2019-07-23	1	-18/+30
*	synth: minor refactoring in netlists.disp_vhdl	Tristan Gingold	2019-07-22	1	-47/+51
*	synth: rework names.	Tristan Gingold	2019-07-22	1	-18/+10
*	synth: improve output (id_extract).	Tristan Gingold	2019-07-20	1	-6/+12
*	synth: improve output (for id_insert).	Tristan Gingold	2019-07-20	1	-11/+18
*	synth: add concatn gate	Tristan Gingold	2019-07-19	1	-3/+14
*	synth: add const_z gate.	Tristan Gingold	2019-07-19	1	-1/+5
*	synth: add > and >= operators (#870)	Pepijn de Vos	2019-07-16	1	-0/+6
*	synth: add Id_Port gate to improve display.	Tristan Gingold	2019-07-10	1	-1/+21
*	synth: display instances in reverse order.	Tristan Gingold	2019-07-10	1	-5/+28
*	synth: handle instantiation (WIP)	Tristan Gingold	2019-07-10	1	-8/+19
*	netlists-disp_vhdl: display initial value of idff.	Tristan Gingold	2019-07-04	1	-19/+32
*	netlists: add reduce_or/reduce_and gates.	Tristan Gingold	2019-07-04	1	-0/+13
*	netlists: add assume gate.	Tristan Gingold	2019-07-04	1	-0/+3
*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	1	-0/+2
*	netlists-disp_vhdl: handle xor.	Tristan Gingold	2019-07-02	1	-0/+2
*	netlists-disp_vhdl: handle dyn_insert, fix mul.	Tristan Gingold	2019-07-01	1	-20/+36
*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	1	-0/+46
*	netlists-disp_vhdl: handle numbers in disp_template.	Tristan Gingold	2019-07-01	1	-14/+22
*	netlists disp_vhdl: rewrite uextend.	Tristan Gingold	2019-07-01	1	-5/+7
*	synth: add ule, fix gate number.	Tristan Gingold	2019-06-30	1	-1/+7
*	synth: disp_vhdl: merge literals.	Tristan Gingold	2019-06-28	1	-88/+129
*	synth: Move get_input_net to netlists.utils.	Tristan Gingold	2019-06-28	1	-1/+1
*	synth: fix disp_vhdl. Can now be analyzed.	Tristan Gingold	2019-06-28	1	-68/+159
*	synth: disp_vhdl: handle mux2	Tristan Gingold	2019-06-28	1	-3/+28
*	synth: add get_input_net helper.	Tristan Gingold	2019-06-28	1	-8/+8
*	synth: disp_vhdl: add disp_template.	Tristan Gingold	2019-06-28	1	-23/+46
*	synth: improve disp_vhdl.	Tristan Gingold	2019-06-28	1	-80/+232
*	netlist-disp_vhdl: display parameters, fix output	Tristan Gingold	2019-06-12	1	-11/+45
*	synth: add disp_vhdl.	Tristan Gingold	2019-05-21	1	-0/+239