| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | synth: add const_z gate. | Tristan Gingold | 2019-07-19 | 1 | -0/+5 |
| * | synth: add Id_Port gate to improve display. | Tristan Gingold | 2019-07-10 | 1 | -0/+2 |
| * | synth: handle simple user function calls. | Tristan Gingold | 2019-07-06 | 1 | -0/+2 |
| * | netlists: allow to build idff without a connected D. | Tristan Gingold | 2019-07-04 | 1 | -0/+1 |
| * | netlists: add reduce_or/reduce_and gates. | Tristan Gingold | 2019-07-04 | 1 | -0/+5 |
| * | netlists: add assume gate. | Tristan Gingold | 2019-07-04 | 1 | -0/+2 |
| * | synth: handle concurrent assertions. | Tristan Gingold | 2019-07-02 | 1 | -0/+3 |
| * | synth: add dyn_insert module. | Tristan Gingold | 2019-07-01 | 1 | -2/+5 |
| * | synth: add syn_extract for dynamic slices. | Tristan Gingold | 2019-06-28 | 1 | -1/+6 |
| * | synth: add insert gate. | Tristan Gingold | 2019-06-24 | 1 | -0/+4 |
| * | synth: use only one edge gate, make it fully abstract. Handle falling_edge. | Tristan Gingold | 2019-05-22 | 1 | -5/+2 |
| * | synth: add adff, iadff. | Tristan Gingold | 2019-04-16 | 1 | -0/+9 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+120 |
