iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	netlists: add enable port to id_mem_rd_sync.	Tristan Gingold	2019-12-05	1	-3/+6
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*	netlists: add Get_Design.	Tristan Gingold	2019-11-28	1	-0/+2
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*	netlists: add dyn_insert_en gate.	Tristan Gingold	2019-11-11	1	-2/+8
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*	synth: extract netlists-folds from netlists-builders.	Tristan Gingold	2019-11-05	1	-26/+0
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*	netlists-builders: add build2_uresize.	Tristan Gingold	2019-11-03	1	-0/+7
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*	netlists: add formal input gates.	Tristan Gingold	2019-10-30	1	-0/+4
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*	synth: create build2_concat from netlists-concat.	Tristan Gingold	2019-10-27	1	-0/+4
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*	synth: generate cover for assertion precedent.	Tristan Gingold	2019-10-21	1	-0/+3
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*	synth: add netlists-memories to extract memories. Still WIP.	Tristan Gingold	2019-10-17	1	-3/+4
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*	netlists: declare memory gates.	Tristan Gingold	2019-10-15	1	-0/+20
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*	netlists: rename id_memidx1 to id_memidx	Tristan Gingold	2019-10-03	1	-2/+2
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*	synth: replace memidx2 by addidx; handle some 2d arrays.	Tristan Gingold	2019-10-03	1	-4/+2
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*	synth: simplify dyn_insert.	Tristan Gingold	2019-10-02	1	-2/+1
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*	synth: simplify id_dyn_extract.	Tristan Gingold	2019-10-02	1	-2/+1
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*	synth: introduce memidx1	Tristan Gingold	2019-10-02	1	-3/+4
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*	netlists: add memidx1 and memidx2 gates.	Tristan Gingold	2019-10-02	1	-0/+8
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*	synth: improve support of arrays or arrays. Fix #955	Tristan Gingold	2019-10-01	1	-2/+2
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*	synth: handle rotate.	Tristan Gingold	2019-09-22	1	-4/+4
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*	synth: Add support for PSL cover directive (#930)	T. Meissner	2019-09-19	1	-0/+3
\| \| \| \| \| \|	* synth: Add support for PSL cover directive * testsuite/synth: Add tests for PSL cover directives
*	synth: add build2_const_vec	Tristan Gingold	2019-09-15	1	-0/+9
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*	synth: handle unsigned shift left.	Tristan Gingold	2019-09-11	1	-0/+5
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*	synth: add const_x gate.	Tristan Gingold	2019-09-11	1	-0/+3
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*	synth: add const_sb32, add smul/umul.	Tristan Gingold	2019-09-07	1	-0/+9
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*	synth: remove insert gate.	Tristan Gingold	2019-08-31	1	-3/+0
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*	synth: improve synth_uresize.	Tristan Gingold	2019-08-31	1	-0/+4
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*	synth: add support for record types.	Tristan Gingold	2019-08-29	1	-0/+5
\| \| \| \|	(WIP: need to fix regression of stmt01).
*	synth: set name to assert/assume gates.	Tristan Gingold	2019-08-20	1	-2/+4
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*	synth: set location on assume/assert gates.	Tristan Gingold	2019-08-20	1	-2/+2
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*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-0/+10
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*	synth: rework names.	Tristan Gingold	2019-07-22	1	-1/+2
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*	synth: add concatn gate	Tristan Gingold	2019-07-19	1	-0/+5
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*	synth: add const_z gate.	Tristan Gingold	2019-07-19	1	-0/+5
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*	synth: add Id_Port gate to improve display.	Tristan Gingold	2019-07-10	1	-0/+2
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*	synth: handle simple user function calls.	Tristan Gingold	2019-07-06	1	-0/+2
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*	netlists: allow to build idff without a connected D.	Tristan Gingold	2019-07-04	1	-0/+1
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*	netlists: add reduce_or/reduce_and gates.	Tristan Gingold	2019-07-04	1	-0/+5
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*	netlists: add assume gate.	Tristan Gingold	2019-07-04	1	-0/+2
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*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	1	-0/+3
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*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	1	-2/+5
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*	synth: add syn_extract for dynamic slices.	Tristan Gingold	2019-06-28	1	-1/+6
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*	synth: add insert gate.	Tristan Gingold	2019-06-24	1	-0/+4
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*	synth: use only one edge gate, make it fully abstract. Handle falling_edge.	Tristan Gingold	2019-05-22	1	-5/+2
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*	synth: add adff, iadff.	Tristan Gingold	2019-04-16	1	-0/+9
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*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+120