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* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-012-273/+296
| | | | For #1416
* vhdl: add force and release tokens. For #1416Tristan Gingold2020-08-012-125/+127
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* ghdl-ls: Fix exceptions crashing language serverHenning Holm2020-07-301-1/+14
| | | | | | | | Previously, the language server crashed on any exceptions raised by the handler methods. Catching and logging these exceptions while notify the user about the error results in a much better user experience. This fixes #1410
* Revert "ghdl-ls: Fix exception crashing language server"Henning Holm2020-07-301-5/+1
| | | | This reverts commit eddb55e8a14e6c40b66ce018b7760767981af79d.
* ghdl-ls: Fix exception crashing language serverHenning Holm2020-07-301-1/+5
| | | | | | | | | Previously, the language server crashed on unhandled symbols with an exception. As ignoring unhandled symbols should be fine, logging this as an error to the logger results in a much better user experience. This fixes #1410
* vhdl_langserver/symbols.py: handle PSL directives and declarations.Tristan Gingold2020-07-281-0/+7
| | | | Fix #1409
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-222-5/+5
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-130/+131
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* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-192-570/+591
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-153-435/+444
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* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-0/+5
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* Synthesis of PSL prev function.Tristan Gingold2020-06-022-5/+5
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* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-023-117/+155
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* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-362/+366
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* vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325Tristan Gingold2020-05-191-37/+37
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* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-161-81/+81
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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-203-15/+9
| | | | Global renaming.
* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-60/+84
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* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-112-339/+341
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* vhdl: handle pragma synthesis_on/synthesis_off.Tristan Gingold2020-04-111-180/+184
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* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-92/+94
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* vhdl: recognize comparaison of std_logic_arith.Tristan Gingold2020-04-111-12/+60
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* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-062-97/+108
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* python: fix document URI creation on Windows (#1183)Maximilian Köstler2020-03-311-1/+1
| | | | On Windows, a URI has to begin with file:/// (3 slashes!). Now, the correct implementation from lsp.py is used to create the URIs.
* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-281-0/+12
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* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-222-283/+288
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* vhdl: recognize minimum/maximum in numeric_std. For #1168Tristan Gingold2020-03-211-164/+176
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* python/setup.py: add missing dependency.Tristan Gingold2020-03-211-0/+6
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* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-77/+79
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* std_names: add *_reduce names.Tristan Gingold2020-03-131-183/+189
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* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-0/+32
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* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-112-183/+188
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* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-162/+174
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-103-169/+179
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* python: update setup.py to install ghdl-lsTristan Gingold2020-03-092-10/+35
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* Import vhdl_langserver from ghdl-language-serverTristan Gingold2020-03-0911-0/+1510
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* [PATCH] Add names for synopsys packages.Tristan Gingold2020-03-032-224/+228
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* Set version to 1.0-devTristan Gingold2020-02-281-1/+1
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* Release 0.37Tristan Gingold2020-02-281-1/+1
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* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-182-405/+415
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* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-205/+209
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* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-90/+126
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* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-71/+72
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* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-140/+144
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* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-77/+85
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* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-103-235/+238
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+28
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-313-101/+126
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-86/+90
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* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-180/+181
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