iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: handle more signed operations. For #1101	Tristan Gingold	2020-01-19	1	-140/+144
\|
*	vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077	Tristan Gingold	2020-01-11	1	-77/+85
\|
*	synth: handle ieee.math_real.round Fix #1075	Tristan Gingold	2020-01-10	3	-235/+238
\|
*	ams-vhdl: add support for 'delayed for quantity.	Tristan Gingold	2019-12-31	1	-25/+28
\|
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	3	-101/+126
\|
*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	1	-86/+90
\|
*	ams-vhdl: add frequency function, minor fixes.	Tristan Gingold	2019-12-30	1	-180/+181
\|
*	ams-vhdl: check nature for record natures and terminals.	Tristan Gingold	2019-12-30	2	-235/+249
\|
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	3	-741/+1004
\|
*	vhdl: add Has_Delay_Machanism for optional 'inertial' printing.	Tristan Gingold	2019-12-26	2	-13/+21
\|
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	2	-345/+348
\|
*	vhdl: recognize sin and cos from math_real.	Tristan Gingold	2019-11-26	2	-225/+229
\|
*	synth: preliminary work to support intrinsic procedures.	Tristan Gingold	2019-11-14	1	-172/+175
\|
*	files_map-editor: add Copy_Source_File.	Tristan Gingold	2019-11-06	1	-0/+2
\|
*	files_map: add Discard_Source_File, Free_Source_File,	Tristan Gingold	2019-11-06	1	-0/+3
\|
*	files_map-editor: turn Replace_Text to a function.	Tristan Gingold	2019-11-06	1	-0/+4
\|
*	vhdl: recognize rising_edge/falling_edge.	Tristan Gingold	2019-11-06	2	-375/+378
\|
*	Add names for formal input gates/attributes.	Tristan Gingold	2019-10-30	1	-167/+173
\|
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	1	-18/+19
\| \| \| \|	Handle more operators in synth.
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	2	-172/+178
\|
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	2	-6/+16
\|
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	1	-22/+27
\|
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	2	-171/+176
\|
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	2	-302/+304
\|
*	vhdl: recognize div operators.	Tristan Gingold	2019-09-30	1	-90/+96
\|
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	2	-217/+223
\|
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	2	-95/+115
\|
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	2	-217/+223
\|
*	vhdl: recognize numeric_std mul.	Tristan Gingold	2019-09-07	1	-82/+88
\|
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	2	-5/+5
\|
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	1	-91/+95
\|
*	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	2	-196/+202
\|
*	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	2	-109/+118
\|
*	synth: handle verification units.	Tristan Gingold	2019-08-20	2	-245/+253
\|
*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	1	-242/+243
\|
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	3	-479/+510
\|
*	vhdl: recognize PSL units reserved words.	Tristan Gingold	2019-08-16	3	-723/+745
\|
*	libghdl: preliminary work to also support synth.	Tristan Gingold	2019-08-13	1	-0/+1
\|
*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	2	-276/+268
\|
*	pnodes.py: be strict about comments, refactoring.	Tristan Gingold	2019-08-07	1	-42/+62
\|
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	2	-110/+117
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	python: regenerate files.	Tristan Gingold	2019-07-26	3	-287/+302
\|
*	libghdl: import Free_Dependence_List.	Tristan Gingold	2019-07-11	1	-0/+2
\|
*	libghdl: automatically set the prefix from shared library	Tristan Gingold	2019-07-09	1	-12/+17
\|
*	python: add errorout_console, disp_config.	Tristan Gingold	2019-07-08	2	-0/+6
\|
*	Fix a merge collision.	Tristan Gingold	2019-07-08	1	-154/+84
\|
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-3/+3
\|
*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	2	-21/+96
\|
*	Move pnodes.py.py to xtools directory.	Tristan Gingold	2019-07-04	1	-3/+0
\|
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	2	-340/+401
\|