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* Change needs to be done in pynodes.Patrick Lehmann2022-12-241-0/+9
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* Improved doc-strings.Patrick Lehmann2022-12-241-0/+3
| | | | (cherry picked from commit 54ce76e3938413f9ee7d823cf63611c4ff5d8faf)
* Tiny fixes.Patrick Lehmann2022-12-241-3/+15
| | | | (cherry picked from commit 2cb36a37f5efa1185ba4c61ea65b49aa6e9345a0)
* pyGHDL: reformattingTristan Gingold2022-12-201-1/+2
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* libghdl: add Get_Source_Identifier_StrTristan Gingold2022-12-201-0/+11
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* vhdl: add Get/Set_Associated_package. For #2264Tristan Gingold2022-12-182-123/+143
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* vhdl-nodes: add Get/Set_Instantiated_Header.Tristan Gingold2022-12-162-144/+164
| | | | For #2264
* vhdl-nodes: add Get/Set_Associated_Subprogram.Tristan Gingold2022-11-302-271/+291
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* pyGHDL: added missing type annotations. Fix #2192 (#2195)fhuemer2022-09-231-2/+2
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* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-212/+213
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* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-111-257/+260
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* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-102-63/+83
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* vhdl: add an owner to interface type definitionTristan Gingold2022-08-072-280/+300
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* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-072-327/+367
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* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-292-19/+39
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* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-252-274/+294
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* vhdl-nodes: renaming.Tristan Gingold2022-07-212-15/+15
| | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-161-4/+12
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* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-122-85/+105
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* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-111-2/+2
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* vhdl-ieee-math_real: recognize more operationsTristan Gingold2022-06-061-218/+240
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* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-061-222/+224
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* vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-051-458/+481
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* vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-051-293/+317
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* vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01zTristan Gingold2022-06-051-226/+234
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* vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostringTristan Gingold2022-06-011-424/+426
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* vhdl: recognize numeric_bit.to_unsignedTristan Gingold2022-05-311-220/+226
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* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-301-147/+147
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* vhdl: recognize subprograms from std.envTristan Gingold2022-05-291-484/+489
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* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-262-2/+66
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* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-178/+180
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* vhdl-nodes: reorder, add iir_kinds_structural_statementTristan Gingold2022-04-291-11/+19
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* vhdl: parse return identifier (v19)Tristan Gingold2022-03-042-228/+248
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* Changed export decorator from pydecor to pyTooling.DecoratorsPatrick Lehmann2021-12-1213-13/+13
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* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-111-280/+284
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* pyGHDL: regenerate nodes.pyTristan Gingold2021-11-101-309/+311
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-5/+0
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-042-377/+378
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* vhdl: add tok_inherit. Preliminary work for #1899Tristan Gingold2021-11-031-52/+53
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* Add parsing of case? statement and simple test.Brian Padalino2021-09-243-238/+259
| | | | Also add the Matching flag to the Iir_Kind_Case_Statement.
* Added binding to new function 'Get_Source_Identifier'.Patrick Lehmann2021-09-161-0/+50
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* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-301-0/+17
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* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-303-31/+53
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-180/+179
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* black: rerun, to pick pyproject settingsumarcor2021-08-233-12/+4
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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-297/+305
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* Fix Codacy problems.Patrick Lehmann2021-07-018-0/+392
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* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-011-1/+0
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* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-563/+565
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* fix more codacy issuesumarcor2021-06-232-4/+1
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