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*
simul: fix signal attribute or guard as actual in connections
Tristan Gingold
2022-10-06
2
-11
/
+15
*
simul: improve debugger (display of signals value)
Tristan Gingold
2022-10-06
4
-38
/
+74
*
simul: handle suspendable procedure call from sensitized process.
Tristan Gingold
2022-10-05
2
-3
/
+11
*
testsuite/synth: add a reproducer for #2205
Tristan Gingold
2022-10-04
2
-0
/
+40
*
elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205
Tristan Gingold
2022-10-04
1
-2
/
+4
*
testsuite/synth: add a test for #2204
Tristan Gingold
2022-10-03
6
-0
/
+158
*
synth: avoid crash on invalid hdl in psl. Fix #2204
Tristan Gingold
2022-10-03
3
-17
/
+46
*
gh action: replace ubuntu 18 by ubuntu 22 (without docker)
Tristan Gingold
2022-10-03
2
-31
/
+51
*
workflow: back to ubuntu 18.
Tristan Gingold
2022-10-03
1
-3
/
+3
*
workflow: use llvm-14 on unbuntu-22
Tristan Gingold
2022-10-02
1
-1
/
+1
*
workflows: tentatively build on ubuntu22
Tristan Gingold
2022-10-02
2
-4
/
+4
*
github actions: use llvm14 on macosx
Tristan Gingold
2022-10-02
1
-1
/
+1
*
translate, grt: add lib function for div and rem.
Tristan Gingold
2022-10-02
6
-8
/
+148
*
synth: improve error recovery
Tristan Gingold
2022-10-02
1
-0
/
+3
*
synth: detect division by 0, handle universal real/integer division
Tristan Gingold
2022-10-02
1
-3
/
+23
*
testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#174
Tristan Gingold
2022-10-02
2
-0
/
+37
*
synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174
Tristan Gingold
2022-10-02
1
-18
/
+204
*
synth: avoid a crash on literal overflow
Tristan Gingold
2022-10-01
1
-1
/
+10
*
synth: avoid on crash on overflow in ranges
Tristan Gingold
2022-10-01
1
-0
/
+8
*
synth: improve handling of individual generic associations
Tristan Gingold
2022-10-01
1
-17
/
+22
*
simul: finalize empty procedures
Tristan Gingold
2022-10-01
1
-9
/
+11
*
simul: minor rewrite
Tristan Gingold
2022-10-01
1
-3
/
+2
*
simul: finalize declarations of procedure calls
Tristan Gingold
2022-10-01
2
-0
/
+6
*
synth: handle read for floats
Tristan Gingold
2022-09-30
2
-8
/
+24
*
synth: handle float-float conversions
Tristan Gingold
2022-09-30
1
-3
/
+14
*
simul: handle stable attribute
Tristan Gingold
2022-09-30
2
-5
/
+44
*
synth: factorize code
Tristan Gingold
2022-09-30
2
-8
/
+9
*
simul: create disconnections
Tristan Gingold
2022-09-30
1
-1
/
+42
*
testsuite/gna: add a test for the previous commit
Tristan Gingold
2022-09-30
2
-0
/
+16
*
libraries.adb: do not set location of entity name of architecture.
Tristan Gingold
2022-09-30
1
-1
/
+0
*
testsuite/gna: add a test for #2193
Tristan Gingold
2022-09-30
3
-0
/
+84
*
testsuite/gna: rename issue and close #2202
Tristan Gingold
2022-09-30
2
-0
/
+0
*
ortho/llvm6: handle llvm 15 (opaque pointers)
Tristan Gingold
2022-09-29
1
-39
/
+64
*
simul: handle quiet attribute
Tristan Gingold
2022-09-29
4
-12
/
+88
*
simul: factorize code, add sub_signal_type
Tristan Gingold
2022-09-29
4
-92
/
+73
*
vhdl-canon: extract guard for signal assignment sensitivity
Tristan Gingold
2022-09-29
1
-1
/
+15
*
simul: support guarded signal assignments (WIP)
Tristan Gingold
2022-09-29
1
-8
/
+79
*
testsuite/gna: adjust baseline
Tristan Gingold
2022-09-29
1
-15
/
+15
*
synth: handle guard signal in debugger
Tristan Gingold
2022-09-28
3
-57
/
+78
*
simul: handle last_value attribute
Tristan Gingold
2022-09-28
3
-1
/
+31
*
synth: handle guard signal in expressions
Tristan Gingold
2022-09-28
2
-0
/
+2
*
simul: fix handling of labels in next/exit statements
Tristan Gingold
2022-09-28
1
-4
/
+13
*
synth: handle null-range loops
Tristan Gingold
2022-09-28
5
-21
/
+40
*
testsuite/gna: add a test for #2201
Tristan Gingold
2022-09-28
2
-0
/
+39
*
vhdl-sem: avoid a crash after error. Fix #2201
Tristan Gingold
2022-09-28
1
-0
/
+1
*
synth: handle names in record aggregate targets
Tristan Gingold
2022-09-28
1
-0
/
+12
*
synth: handle array target aggregate
Tristan Gingold
2022-09-27
1
-2
/
+6
*
synth: handle error on variable default value
Tristan Gingold
2022-09-27
1
-0
/
+5
*
simul: handle null signal assignments
Tristan Gingold
2022-09-27
1
-12
/
+36
*
synth-vhdl_eval: handle nor, nand
Tristan Gingold
2022-09-26
1
-0
/
+21
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