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* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
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* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
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* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-123-1/+9
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* testsuite/synth: add tests for succ/pred/leftof/rightof attributesTristan Gingold2022-09-129-0/+113
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* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
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* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-117-20/+58
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* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
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* simul: move assertions (not to trigger in case of errors)Tristan Gingold2022-09-111-3/+3
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* simul: optimize resolution call only for std_logicTristan Gingold2022-09-111-5/+11
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* synth: fix and add checks for memory management.Tristan Gingold2022-09-1016-116/+362
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* testsuite/synth: add a test with uninitialized shared variableTristan Gingold2022-09-083-1/+101
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* simul: add support for protected objectsTristan Gingold2022-09-0812-23/+267
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* testsuite/synth: add a test for #2187Tristan Gingold2022-09-085-0/+410
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* elab-vhdl_objtypes: handle bounded array base type. Fix #2187Tristan Gingold2022-09-081-1/+2
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* elab-vhdl_values: factorize codeTristan Gingold2022-09-076-29/+16
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* simul: do not propagate errors from resolution functionTristan Gingold2022-09-071-0/+3
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* synth-vhdl_stmts: fix handling of copyback parametersTristan Gingold2022-09-073-26/+38
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* elab-vhdl_stmts: fix a TODOTristan Gingold2022-09-071-1/+3
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* synth: handle open entity aspectTristan Gingold2022-09-071-4/+4
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* elab-vhdl_heap: fix handling of simple access typesTristan Gingold2022-09-071-4/+17
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* simul: fix computation for number of driversTristan Gingold2022-09-061-1/+2
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* synth: handle generics in blocksTristan Gingold2022-09-064-10/+53
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* simul: add an hook to display report/assert messageTristan Gingold2022-09-063-50/+128
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* synth-vhdl_eval: handle std_logic_signed and std_logic_unsignedTristan Gingold2022-09-061-55/+111
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* synth: add evaluation for ieee.std_logic_arithTristan Gingold2022-09-056-43/+1181
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* testsuite/gna: add a test for #2185Tristan Gingold2022-09-028-0/+969
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* grt: add a SIGFPE handler for linux x86/64. Fix #2185Tristan Gingold2022-09-021-0/+4
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* synth: extract synth-ieee-utils from synth-ieee-numeric_stdTristan Gingold2022-09-022-21/+46
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* testsuite/synth: improve test #1460Tristan Gingold2022-09-022-0/+18
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* synth: improve debug subprogramsTristan Gingold2022-09-022-1/+8
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* synth: use areapoolsTristan Gingold2022-09-0230-269/+981
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* synth: factorize code for tracing statements executionTristan Gingold2022-09-024-16/+23
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* simul: detect multiple drivers for unresolved signalsTristan Gingold2022-09-021-8/+93
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* doc: update URL to IEEE 1076 standardPatrick Lehmann2022-08-291-1/+1
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| * doc: update URL to IEEE 1076 standardEmanuele Torre2022-08-291-1/+1
|/ | | That page has been moved, and the old URL now results in a 404 error.
* simul-vhdl_simul: simplify procedure connectTristan Gingold2022-08-261-41/+22
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* vhdl-sem_assocs: improve error messageTristan Gingold2022-08-251-1/+1
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* synth: handle component aspect configurationTristan Gingold2022-08-251-1/+5
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* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
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* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-252-5/+30
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* synth: handle unbounded top-level portsTristan Gingold2022-08-251-9/+18
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* synth: handle type left/right attributesTristan Gingold2022-08-253-0/+26
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* simul: improve support of float signalsTristan Gingold2022-08-241-3/+7
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* grt-disp_signals: also disp conversions rangesTristan Gingold2022-08-241-0/+11
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* simul: handle conversions and associations with constantsTristan Gingold2022-08-242-70/+399
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* simul: simplify codeTristan Gingold2022-08-232-16/+7
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* simul: factorize code to compute number of sourcesTristan Gingold2022-08-234-120/+50
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* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
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* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-233-14/+152
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* elab: add default value to portsTristan Gingold2022-08-234-13/+28
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