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* synth: handle component aspect configurationTristan Gingold2022-08-251-1/+5
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* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
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* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-252-5/+30
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* synth: handle unbounded top-level portsTristan Gingold2022-08-251-9/+18
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* synth: handle type left/right attributesTristan Gingold2022-08-253-0/+26
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* simul: improve support of float signalsTristan Gingold2022-08-241-3/+7
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* grt-disp_signals: also disp conversions rangesTristan Gingold2022-08-241-0/+11
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* simul: handle conversions and associations with constantsTristan Gingold2022-08-242-70/+399
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* simul: simplify codeTristan Gingold2022-08-232-16/+7
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* simul: factorize code to compute number of sourcesTristan Gingold2022-08-234-120/+50
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* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
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* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-233-14/+152
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* elab: add default value to portsTristan Gingold2022-08-234-13/+28
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* grt-signals: add ghdl_signal_add_extra_driverTristan Gingold2022-08-232-0/+19
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* grt-signals: internal refactoring for drivers creationTristan Gingold2022-08-221-25/+39
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* synth-vhdl_static_proc: handle std.env.finishTristan Gingold2022-08-211-1/+2
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* simul-vhdl_simul: handle waveforms in signal assignmentsTristan Gingold2022-08-212-40/+51
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* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-219-53/+35
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* grt-errors: remove error_hook (was unused)Tristan Gingold2022-08-212-14/+0
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* simul: rework assertions execution and error handlingTristan Gingold2022-08-215-10/+13
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* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
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* simul: handle after clauses in signal assignmentTristan Gingold2022-08-213-70/+111
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* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-204-34/+289
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* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
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* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
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* simul: handle resolved signals (WIP)Tristan Gingold2022-08-194-49/+332
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* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-183-3/+6
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* testsuite/gna: add a test and close #2179Tristan Gingold2022-08-182-0/+48
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* simul: handle individual associationsTristan Gingold2022-08-172-4/+16
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* simul: add create_connectsTristan Gingold2022-08-174-46/+144
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* simul: create terminals (WIP)Tristan Gingold2022-08-174-8/+62
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* suite_driver: avoid spurious error messages, fix --list-filesTristan Gingold2022-08-161-2/+2
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* elab-vhdl_objtypes: handle holes in comparisons.Tristan Gingold2022-08-161-7/+72
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* netlists-memories: add a TODO commentTristan Gingold2022-08-161-0/+8
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* synth/netlists: add commentsTristan Gingold2022-08-162-7/+14
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* testsuite/synth: add more tests for memoryTristan Gingold2022-08-165-0/+217
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* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
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* netlists-memories: renaming and add commentsTristan Gingold2022-08-161-25/+38
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* psl-rewrites: minor style changeTristan Gingold2022-08-161-2/+1
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* gdbinit: add ppsltfTristan Gingold2022-08-151-0/+8
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* vhdl-prints: improve handling of PSL. For #2178Tristan Gingold2022-08-156-63/+184
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* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-1514-438/+505
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* pyGHDL: update bindingsTristan Gingold2022-08-151-201/+203
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* testsuite/synth: add a test for #2177Tristan Gingold2022-08-145-0/+2768
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* elab-vhdl_values-debug: improve output of debug_valtypTristan Gingold2022-08-141-1/+3
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* synth-vhdl_context: fix handling of alias in get_net. Fix #2177Tristan Gingold2022-08-141-4/+3
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* testsuite/synth: add a test for #2176Tristan Gingold2022-08-142-0/+30
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* vhdl: recognize log10 and sqrt from math_real. Fix #2176Tristan Gingold2022-08-144-10/+32
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* testsuite/synth: add a test for previous commitTristan Gingold2022-08-143-1/+82
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* synth: handle assignment to record aggregateTristan Gingold2022-08-142-31/+109
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