iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl-scanner: handle 'synopsys' pragma.	Tristan Gingold	2019-11-04	3	-16/+19
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*	ghdlmain: fix deallocation in response file handling.	Tristan Gingold	2019-11-04	1	-0/+10
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*	Add doc of the 3 ways to use PSL with GHDL (Implementation of VHDL -> PSL ↵	T. Meissner	2019-11-03	1	-15/+84
\| \| \| \|	implementation) (#996)
*	netlists-expands: expand rol.	Tristan Gingold	2019-11-03	1	-0/+30
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*	synth-oper: use build2_uresize	Tristan Gingold	2019-11-03	1	-16/+2
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*	netlists-utils: add clog2	Tristan Gingold	2019-11-03	2	-0/+8
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*	netlists-builders: add build2_uresize.	Tristan Gingold	2019-11-03	2	-0/+31
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*	synth: fix multiport read memories (for issue #1000)	Tristan Gingold	2019-11-03	1	-1/+3
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*	testsuite/synth: add a test for ram/rom.	Tristan Gingold	2019-11-03	5	-0/+154
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*	testsuite/synth: add test for tgingold/ghdlsynth-beta#56	Tristan Gingold	2019-11-03	3	-0/+58
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*	testsuite/synth/memmux01: add a test	Tristan Gingold	2019-11-03	3	-1/+98
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*	testsuite/synth/var01: add more tests.	Tristan Gingold	2019-11-03	8	-2/+233
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*	synth: cap max in synth_slice_suffix	Tristan Gingold	2019-11-03	1	-1/+8
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*	netlists-expands: rewrite generate_muxes.	Tristan Gingold	2019-11-03	1	-24/+102
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*	testsuite/synth: add memmux04 test.	Tristan Gingold	2019-11-03	3	-1/+75
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*	netlists-expands: use a safe walk.	Tristan Gingold	2019-11-03	1	-1/+3
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*	Install source of std.standard package to respective VHDL standard version ↵	Torsten Maehne	2019-11-02	1	-3/+3
\| \| \| \|	sub-directories (#995)
*	testsuite/synth: add a test for inout variable	Tristan Gingold	2019-11-01	3	-0/+64
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*	synth: add support for inout variable interfaces.	Tristan Gingold	2019-11-01	2	-3/+4
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*	synth-values: handle value_const for is_equal.	Tristan Gingold	2019-11-01	1	-0/+5
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*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2019-11-01	3	-1/+68
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*	synth: handle nested if generate statements.	Tristan Gingold	2019-11-01	2	-21/+29
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*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2019-11-01	3	-1/+123
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*	netlits: fix memidx order.	Tristan Gingold	2019-11-01	2	-39/+52
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*	netlists-dump: improve output.	Tristan Gingold	2019-11-01	1	-10/+11
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*	testsuite/synth: add a test for dyn_insert expand.	Tristan Gingold	2019-11-01	2	-1/+71
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*	netlists-expands: expand dyn_insert	Tristan Gingold	2019-11-01	2	-42/+174
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*	testsuite/synth: add testcase for psl.	Tristan Gingold	2019-10-31	7	-0/+79
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*	psl-nfa-utils: move active state in merge_state.	Tristan Gingold	2019-10-31	1	-0/+5
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*	vhdl-prints: handle more constructs in psl vunit.	Tristan Gingold	2019-10-31	1	-0/+5
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*	ghdlsynth_gates.h: regenerate.	Tristan Gingold	2019-10-31	1	-0/+4
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*	synth: handle attributes in vunit.	Tristan Gingold	2019-10-30	1	-1/+86
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*	netlists: add formal input gates.	Tristan Gingold	2019-10-30	3	-0/+44
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*	vhdl: allow attributes in vunit declarations.	Tristan Gingold	2019-10-30	6	-200/+216
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*	Add names for formal input gates/attributes.	Tristan Gingold	2019-10-30	3	-168/+186
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*	netlists-expands: handle 2d arrays.	Tristan Gingold	2019-10-28	1	-83/+72
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*	synth: adjust computation of max for dyn_extract.	Tristan Gingold	2019-10-28	3	-8/+10
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*	netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.	Tristan Gingold	2019-10-28	1	-1/+3
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*	testsuite/synth: add tests for dyn_extract expand.	Tristan Gingold	2019-10-28	6	-0/+245
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*	synth-expr (synth_slice_suffix): compute max value for slices.	Tristan Gingold	2019-10-27	1	-1/+4
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*	netlists-expand: truncate address if needed.	Tristan Gingold	2019-10-27	1	-0/+10
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*	ghdlsynth: add -de option.	Tristan Gingold	2019-10-27	1	-0/+3
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*	netlists: add code to expand dyn_extract gates (WIP).	Tristan Gingold	2019-10-27	5	-1/+259
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*	netlists: change Loc parameter of synth_case.	Tristan Gingold	2019-10-27	5	-6/+21
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*	synth: create build2_concat from netlists-concat.	Tristan Gingold	2019-10-27	7	-38/+48
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*	netlists-butils: extract synth_case from synth.stmts.	Tristan Gingold	2019-10-26	3	-149/+206
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*	testsuite/synth/psl02: renaming.	Tristan Gingold	2019-10-26	1	-1/+1
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*	synth: handle concurrent signal assignment in vunits.	Tristan Gingold	2019-10-25	2	-83/+91
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*	vhdl-canon: handle simple signal assignment in vunits.	Tristan Gingold	2019-10-25	1	-273/+272
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*	vhdl-canon: extract canon_concurrent_label.	Tristan Gingold	2019-10-25	1	-20/+25
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