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* synth: cap max in synth_slice_suffixTristan Gingold2019-11-031-1/+8
* netlists-expands: rewrite generate_muxes.Tristan Gingold2019-11-031-24/+102
* testsuite/synth: add memmux04 test.Tristan Gingold2019-11-033-1/+75
* netlists-expands: use a safe walk.Tristan Gingold2019-11-031-1/+3
* Install source of std.standard package to respective VHDL standard version su...Torsten Maehne2019-11-021-3/+3
* testsuite/synth: add a test for inout variableTristan Gingold2019-11-013-0/+64
* synth: add support for inout variable interfaces.Tristan Gingold2019-11-012-3/+4
* synth-values: handle value_const for is_equal.Tristan Gingold2019-11-011-0/+5
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-013-1/+68
* synth: handle nested if generate statements.Tristan Gingold2019-11-012-21/+29
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-013-1/+123
* netlits: fix memidx order.Tristan Gingold2019-11-012-39/+52
* netlists-dump: improve output.Tristan Gingold2019-11-011-10/+11
* testsuite/synth: add a test for dyn_insert expand.Tristan Gingold2019-11-012-1/+71
* netlists-expands: expand dyn_insertTristan Gingold2019-11-012-42/+174
* testsuite/synth: add testcase for psl.Tristan Gingold2019-10-317-0/+79
* psl-nfa-utils: move active state in merge_state.Tristan Gingold2019-10-311-0/+5
* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
* ghdlsynth_gates.h: regenerate.Tristan Gingold2019-10-311-0/+4
* synth: handle attributes in vunit.Tristan Gingold2019-10-301-1/+86
* netlists: add formal input gates.Tristan Gingold2019-10-303-0/+44
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-306-200/+216
* Add names for formal input gates/attributes.Tristan Gingold2019-10-303-168/+186
* netlists-expands: handle 2d arrays.Tristan Gingold2019-10-281-83/+72
* synth: adjust computation of max for dyn_extract.Tristan Gingold2019-10-283-8/+10
* netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.Tristan Gingold2019-10-281-1/+3
* testsuite/synth: add tests for dyn_extract expand.Tristan Gingold2019-10-286-0/+245
* synth-expr (synth_slice_suffix): compute max value for slices.Tristan Gingold2019-10-271-1/+4
* netlists-expand: truncate address if needed.Tristan Gingold2019-10-271-0/+10
* ghdlsynth: add -de option.Tristan Gingold2019-10-271-0/+3
* netlists: add code to expand dyn_extract gates (WIP).Tristan Gingold2019-10-275-1/+259
* netlists: change Loc parameter of synth_case.Tristan Gingold2019-10-275-6/+21
* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-277-38/+48
* netlists-butils: extract synth_case from synth.stmts.Tristan Gingold2019-10-263-149/+206
* testsuite/synth/psl02: renaming.Tristan Gingold2019-10-261-1/+1
* synth: handle concurrent signal assignment in vunits.Tristan Gingold2019-10-252-83/+91
* vhdl-canon: handle simple signal assignment in vunits.Tristan Gingold2019-10-251-273/+272
* vhdl-canon: extract canon_concurrent_label.Tristan Gingold2019-10-251-20/+25
* vhdl-annotations: extract annotate_concurrent_statement.Tristan Gingold2019-10-251-47/+53
* vhdl-annotations: minor renaming.Tristan Gingold2019-10-251-8/+8
* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-254-119/+122
* vhdl-parse_psl: add comments.Tristan Gingold2019-10-251-8/+71
* Add testcase for previous commit.Tristan Gingold2019-10-242-0/+15
* vhdl-parse: do not scan PSL keywords in vunit declarations.Tristan Gingold2019-10-241-0/+4
* configure: fails if 'make' failed.Tristan Gingold2019-10-241-1/+4
* Add testcase for #984Tristan Gingold2019-10-246-0/+62
* vhdl/translate: elaborate dependencies of configurations. Fix #984Tristan Gingold2019-10-241-0/+4
* configure: fix typo (#994)1138-4EB2019-10-231-1/+1
* synth: add support for declarations in vunits.Tristan Gingold2019-10-232-4/+27
* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4