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* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-0511-160/+216
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* netlists-dump: indent output.Tristan Gingold2019-11-053-13/+17
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* netlists-memories: adjust message.Tristan Gingold2019-11-051-1/+1
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* testsuite/synth: add testcase for #1002.Tristan Gingold2019-11-042-0/+26
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* netlists: enable expansion.Tristan Gingold2019-11-041-1/+1
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* synth-oper: handle constant not.Tristan Gingold2019-11-041-3/+8
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* synth-expr: allow constants in discrete rangeTristan Gingold2019-11-041-0/+2
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* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-043-0/+56
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* synth-expr: handle vhdl 2008 aggregates (partially).Tristan Gingold2019-11-042-48/+125
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* synth-value: export get_bound_length.Tristan Gingold2019-11-041-0/+3
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* ghdlmain: simplify code.Tristan Gingold2019-11-041-4/+1
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* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-043-16/+19
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* ghdlmain: fix deallocation in response file handling.Tristan Gingold2019-11-041-0/+10
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* Add doc of the 3 ways to use PSL with GHDL (Implementation of VHDL -> PSL ↵T. Meissner2019-11-031-15/+84
| | | | implementation) (#996)
* netlists-expands: expand rol.Tristan Gingold2019-11-031-0/+30
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* synth-oper: use build2_uresizeTristan Gingold2019-11-031-16/+2
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* netlists-utils: add clog2Tristan Gingold2019-11-032-0/+8
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* netlists-builders: add build2_uresize.Tristan Gingold2019-11-032-0/+31
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* synth: fix multiport read memories (for issue #1000)Tristan Gingold2019-11-031-1/+3
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* testsuite/synth: add a test for ram/rom.Tristan Gingold2019-11-035-0/+154
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* testsuite/synth: add test for tgingold/ghdlsynth-beta#56Tristan Gingold2019-11-033-0/+58
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* testsuite/synth/memmux01: add a testTristan Gingold2019-11-033-1/+98
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* testsuite/synth/var01: add more tests.Tristan Gingold2019-11-038-2/+233
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* synth: cap max in synth_slice_suffixTristan Gingold2019-11-031-1/+8
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* netlists-expands: rewrite generate_muxes.Tristan Gingold2019-11-031-24/+102
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* testsuite/synth: add memmux04 test.Tristan Gingold2019-11-033-1/+75
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* netlists-expands: use a safe walk.Tristan Gingold2019-11-031-1/+3
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* Install source of std.standard package to respective VHDL standard version ↵Torsten Maehne2019-11-021-3/+3
| | | | sub-directories (#995)
* testsuite/synth: add a test for inout variableTristan Gingold2019-11-013-0/+64
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* synth: add support for inout variable interfaces.Tristan Gingold2019-11-012-3/+4
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* synth-values: handle value_const for is_equal.Tristan Gingold2019-11-011-0/+5
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* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-013-1/+68
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* synth: handle nested if generate statements.Tristan Gingold2019-11-012-21/+29
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* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-013-1/+123
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* netlits: fix memidx order.Tristan Gingold2019-11-012-39/+52
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* netlists-dump: improve output.Tristan Gingold2019-11-011-10/+11
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* testsuite/synth: add a test for dyn_insert expand.Tristan Gingold2019-11-012-1/+71
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* netlists-expands: expand dyn_insertTristan Gingold2019-11-012-42/+174
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* testsuite/synth: add testcase for psl.Tristan Gingold2019-10-317-0/+79
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* psl-nfa-utils: move active state in merge_state.Tristan Gingold2019-10-311-0/+5
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* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
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* ghdlsynth_gates.h: regenerate.Tristan Gingold2019-10-311-0/+4
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* synth: handle attributes in vunit.Tristan Gingold2019-10-301-1/+86
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* netlists: add formal input gates.Tristan Gingold2019-10-303-0/+44
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* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-306-200/+216
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* Add names for formal input gates/attributes.Tristan Gingold2019-10-303-168/+186
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* netlists-expands: handle 2d arrays.Tristan Gingold2019-10-281-83/+72
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* synth: adjust computation of max for dyn_extract.Tristan Gingold2019-10-283-8/+10
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* netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.Tristan Gingold2019-10-281-1/+3
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* testsuite/synth: add tests for dyn_extract expand.Tristan Gingold2019-10-286-0/+245
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