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*
synth: add evaluation for ieee.std_logic_arith
Tristan Gingold
2022-09-05
6
-43
/
+1181
*
testsuite/gna: add a test for #2185
Tristan Gingold
2022-09-02
8
-0
/
+969
*
grt: add a SIGFPE handler for linux x86/64. Fix #2185
Tristan Gingold
2022-09-02
1
-0
/
+4
*
synth: extract synth-ieee-utils from synth-ieee-numeric_std
Tristan Gingold
2022-09-02
2
-21
/
+46
*
testsuite/synth: improve test #1460
Tristan Gingold
2022-09-02
2
-0
/
+18
*
synth: improve debug subprograms
Tristan Gingold
2022-09-02
2
-1
/
+8
*
synth: use areapools
Tristan Gingold
2022-09-02
30
-269
/
+981
*
synth: factorize code for tracing statements execution
Tristan Gingold
2022-09-02
4
-16
/
+23
*
simul: detect multiple drivers for unresolved signals
Tristan Gingold
2022-09-02
1
-8
/
+93
*
doc: update URL to IEEE 1076 standard
Patrick Lehmann
2022-08-29
1
-1
/
+1
|
\
|
*
doc: update URL to IEEE 1076 standard
Emanuele Torre
2022-08-29
1
-1
/
+1
|
/
*
simul-vhdl_simul: simplify procedure connect
Tristan Gingold
2022-08-26
1
-41
/
+22
*
vhdl-sem_assocs: improve error message
Tristan Gingold
2022-08-25
1
-1
/
+1
*
synth: handle component aspect configuration
Tristan Gingold
2022-08-25
1
-1
/
+5
*
simul: handle connections of records
Tristan Gingold
2022-08-25
1
-1
/
+18
*
synth: handle indexes/ranges in configurations for generate blocks
Tristan Gingold
2022-08-25
2
-5
/
+30
*
synth: handle unbounded top-level ports
Tristan Gingold
2022-08-25
1
-9
/
+18
*
synth: handle type left/right attributes
Tristan Gingold
2022-08-25
3
-0
/
+26
*
simul: improve support of float signals
Tristan Gingold
2022-08-24
1
-3
/
+7
*
grt-disp_signals: also disp conversions ranges
Tristan Gingold
2022-08-24
1
-0
/
+11
*
simul: handle conversions and associations with constants
Tristan Gingold
2022-08-24
2
-70
/
+399
*
simul: simplify code
Tristan Gingold
2022-08-23
2
-16
/
+7
*
simul: factorize code to compute number of sources
Tristan Gingold
2022-08-23
4
-120
/
+50
*
simul-vhdl_debug: disp nbr sources
Tristan Gingold
2022-08-23
1
-1
/
+15
*
simul: add extra drivers for ports without sources
Tristan Gingold
2022-08-23
3
-14
/
+152
*
elab: add default value to ports
Tristan Gingold
2022-08-23
4
-13
/
+28
*
grt-signals: add ghdl_signal_add_extra_driver
Tristan Gingold
2022-08-23
2
-0
/
+19
*
grt-signals: internal refactoring for drivers creation
Tristan Gingold
2022-08-22
1
-25
/
+39
*
synth-vhdl_static_proc: handle std.env.finish
Tristan Gingold
2022-08-21
1
-1
/
+2
*
simul-vhdl_simul: handle waveforms in signal assignments
Tristan Gingold
2022-08-21
2
-40
/
+51
*
synth: factorize code for synth_subtype_conversion
Tristan Gingold
2022-08-21
9
-53
/
+35
*
grt-errors: remove error_hook (was unused)
Tristan Gingold
2022-08-21
2
-14
/
+0
*
simul: rework assertions execution and error handling
Tristan Gingold
2022-08-21
5
-10
/
+13
*
simul: handle concurrent procedure calls (WIP)
Tristan Gingold
2022-08-21
1
-15
/
+95
*
simul: handle after clauses in signal assignment
Tristan Gingold
2022-08-21
3
-70
/
+111
*
simul-vhdl_simul: add support for PSL directives
Tristan Gingold
2022-08-20
4
-34
/
+289
*
elab-vhdl_expr: factorize code
Tristan Gingold
2022-08-19
10
-998
/
+50
*
simul-vhdl_debug: display connections
Tristan Gingold
2022-08-19
1
-5
/
+63
*
simul: handle resolved signals (WIP)
Tristan Gingold
2022-08-19
4
-49
/
+332
*
ghdlsimul: add an option to debug before elaboration
Tristan Gingold
2022-08-18
3
-3
/
+6
*
testsuite/gna: add a test and close #2179
Tristan Gingold
2022-08-18
2
-0
/
+48
*
simul: handle individual associations
Tristan Gingold
2022-08-17
2
-4
/
+16
*
simul: add create_connects
Tristan Gingold
2022-08-17
4
-46
/
+144
*
simul: create terminals (WIP)
Tristan Gingold
2022-08-17
4
-8
/
+62
*
suite_driver: avoid spurious error messages, fix --list-files
Tristan Gingold
2022-08-16
1
-2
/
+2
*
elab-vhdl_objtypes: handle holes in comparisons.
Tristan Gingold
2022-08-16
1
-7
/
+72
*
netlists-memories: add a TODO comment
Tristan Gingold
2022-08-16
1
-0
/
+8
*
synth/netlists: add comments
Tristan Gingold
2022-08-16
2
-7
/
+14
*
testsuite/synth: add more tests for memory
Tristan Gingold
2022-08-16
5
-0
/
+217
*
synth-vhdl_expr: optimize record with one element.
Tristan Gingold
2022-08-16
1
-3
/
+3
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