| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | readme: add cii best practices badge/shield (#923) | 1138-4EB | 2019-09-18 | 1 | -0/+2 | |
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| * | enhance documentation terminology: reduce name clashing for VHDL standard ↵ | Arcturus | 2019-09-18 | 4 | -6176/+28 | |
| | | | | | | | | | | | | | and collections. (#925) * enhance documentation terminology: reduce name clashing for VHDL standard and collections. * lists don't have columns * apply suggestions from review * remove build artifact | |||||
| * | Add missing file for previous commit. | Tristan Gingold | 2019-09-17 | 2 | -0/+62 | |
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| * | testsuite/synth: add a test for previous commit. | Tristan Gingold | 2019-09-17 | 1 | -1/+1 | |
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| * | synth: fix to get_current_assign_value. | Tristan Gingold | 2019-09-17 | 1 | -7/+4 | |
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| * | netlists-dump: add width on extract output. | Tristan Gingold | 2019-09-17 | 1 | -5/+14 | |
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| * | synth: add debug flag -dc to not clean. | Tristan Gingold | 2019-09-17 | 3 | -1/+9 | |
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| * | testsuite/synth: add var01 | Tristan Gingold | 2019-09-17 | 11 | -0/+384 | |
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| * | synth-inference: detect false loop. | Tristan Gingold | 2019-09-17 | 6 | -2/+335 | |
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| * | synth: fold addition on constant nets. | Tristan Gingold | 2019-09-17 | 10 | -49/+178 | |
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| * | synth: add synth-flags, add debug option -di. | Tristan Gingold | 2019-09-17 | 3 | -1/+32 | |
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| * | synth: minor refactoring about const gates. | Tristan Gingold | 2019-09-15 | 4 | -40/+41 | |
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| * | testsuite/synth: add a test for std_match | Tristan Gingold | 2019-09-15 | 3 | -1/+44 | |
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| * | synth-oper: add support of std_match | Tristan Gingold | 2019-09-15 | 1 | -0/+94 | |
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| * | synth-disp_vhdl: improve support of boolean, suv. | Tristan Gingold | 2019-09-15 | 1 | -17/+16 | |
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| * | synth: add build2_const_vec | Tristan Gingold | 2019-09-15 | 2 | -0/+27 | |
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| * | synth-stmts: fix uninitialized variable. | Tristan Gingold | 2019-09-13 | 1 | -1/+9 | |
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| * | testsuite/synth: add more tests in func01. | Tristan Gingold | 2019-09-13 | 9 | -1/+214 | |
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| * | synth: initialize subprogram variables. | Tristan Gingold | 2019-09-13 | 4 | -8/+14 | |
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| * | synth: remove get_width from synth-expr | Tristan Gingold | 2019-09-12 | 3 | -15/+2 | |
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| * | synth: extract synth-oper from synth-expr | Tristan Gingold | 2019-09-12 | 6 | -927/+1012 | |
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| * | synth: handle simple_aggregate. | Tristan Gingold | 2019-09-12 | 1 | -0/+41 | |
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| * | synth: allow empty string literal. | Tristan Gingold | 2019-09-12 | 2 | -2/+4 | |
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| * | vhdl-nodes: add a comment. | Tristan Gingold | 2019-09-12 | 1 | -1/+1 | |
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| * | synth: handle unsigned shift right | Tristan Gingold | 2019-09-11 | 1 | -0/+7 | |
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| * | vhdl-ieee-numeric: recognize shift_right. | Tristan Gingold | 2019-09-11 | 1 | -17/+31 | |
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| * | synth: handle unsigned shift left. | Tristan Gingold | 2019-09-11 | 5 | -107/+163 | |
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| * | synth: add synth_compare_sgn_sgn | Tristan Gingold | 2019-09-11 | 1 | -0/+23 | |
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| * | synth: handle constant bit compare. | Tristan Gingold | 2019-09-11 | 1 | -0/+6 | |
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| * | synth: handle numeric_std.resize for signed. | Tristan Gingold | 2019-09-11 | 1 | -0/+15 | |
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| * | testsuite/synth: add one more test in ret01 | Tristan Gingold | 2019-09-11 | 3 | -4/+38 | |
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| * | testsuite/synth: add ret01 tests. | Tristan Gingold | 2019-09-11 | 7 | -1/+129 | |
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| * | synth: improve support of return statement. | Tristan Gingold | 2019-09-11 | 8 | -21/+117 | |
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| * | synth: improve support of negative integer values. | Tristan Gingold | 2019-09-11 | 2 | -15/+29 | |
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| * | synth: add const_x gate. | Tristan Gingold | 2019-09-11 | 4 | -1/+27 | |
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| * | synth: introduce Seq_Context. | Tristan Gingold | 2019-09-11 | 2 | -68/+87 | |
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| * | synth: move synth_user_function_call to synth-stmts. | Tristan Gingold | 2019-09-11 | 3 | -60/+62 | |
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| * | testsuite/synth: add a test for slices. | Tristan Gingold | 2019-09-11 | 3 | -2/+63 | |
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| * | synth: improve support of slices. | Tristan Gingold | 2019-09-11 | 1 | -50/+54 | |
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| * | testsuite/synth: add mem02 | Tristan Gingold | 2019-09-11 | 3 | -0/+84 | |
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| * | synth: introduce slice type. | Tristan Gingold | 2019-09-11 | 4 | -1/+26 | |
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| * | testsuite/synth: rename arr02 to mem01 | Tristan Gingold | 2019-09-11 | 9 | -0/+0 | |
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| * | synth: Add width field in type_type record. | Tristan Gingold | 2019-09-11 | 6 | -109/+119 | |
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| * | synth: handle alias (WIP, read only). | Tristan Gingold | 2019-09-11 | 7 | -12/+86 | |
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| * | vhdl: recognize numeric_std shift_left. | Tristan Gingold | 2019-09-11 | 6 | -220/+254 | |
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| * | fix: skip testsuite/sanity/005examples when 'docs' not found (#921) | 1138-4EB | 2019-09-11 | 1 | -0/+6 | |
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| * | synth: add const_sb32, add smul/umul. | Tristan Gingold | 2019-09-07 | 6 | -13/+105 | |
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| * | vhdl: recognize numeric_std mul. | Tristan Gingold | 2019-09-07 | 3 | -82/+115 | |
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| * | testsuite/synth: add testcase for previous commit. | Tristan Gingold | 2019-09-07 | 3 | -0/+77 | |
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| * | synth: handle partial assignments in case statements. | Tristan Gingold | 2019-09-07 | 3 | -44/+95 | |
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index : iCE40/ghdl | |
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