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* Bumped Python package dependencies in pyGHDL.Patrick Lehmann2022-06-183-7/+7
* Fixed failing sanity checks for pyGHDL.dom in coverage job.Patrick Lehmann2022-06-182-4/+6
* Bumped dependency of pyVHDLModel to latest release.Patrick Lehmann2022-06-182-2/+2
* Workaround for Application class.Patrick Lehmann2022-06-181-6/+2
* Bumped dependencies to support pyTooling ≥2.0.Patrick Lehmann2022-06-182-3/+3
* doc: document all warningsTristan Gingold2022-06-171-23/+122
* testsuite/synth: add a test for #2099Tristan Gingold2022-06-162-0/+39
* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
* testsuite/gna: add a test for #2098Tristan Gingold2022-06-162-0/+167
* vhdl-sem.adb(are_trees_equal): handle simple aggregate.Tristan Gingold2022-06-161-14/+12
* testsuite/gna: add a test for #2065Tristan Gingold2022-06-164-0/+742
* vhdl/translate: handle inertial association in recursive instantiationTristan Gingold2022-06-162-2/+16
* testsuite/gna: add a test for #2097Tristan Gingold2022-06-166-0/+209
* vhdl-sem_names: handle element and subtype attributes for type conv.Tristan Gingold2022-06-161-22/+26
* vhdl-sem_expr: do not attribute element or subtype attributes as expr.Tristan Gingold2022-06-161-0/+2
* testsuite/gna: add a test for #2071Tristan Gingold2022-06-154-0/+111
* vhdl: handle 'element in 'range. Fix #2071Tristan Gingold2022-06-152-23/+104
* Add commentsTristan Gingold2022-06-152-1/+2
* testsuite/synth: add a test for #2093Tristan Gingold2022-06-153-1/+54
* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
* testsuite/synth: add a test for #2054Tristan Gingold2022-06-142-0/+27
* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-144-2/+132
* testsuite/synth: add a test for #2092Tristan Gingold2022-06-132-0/+36
* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
* Merge pull request #2094 from antonblanchard/synth-verilog-blockingtgingold2022-06-131-10/+10
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| * netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
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* testsuite/gna: add a test for #2091Tristan Gingold2022-06-123-0/+117
* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-123-265/+271
* testsuite/synth: add a test. close #2080Tristan Gingold2022-06-123-0/+62
* testsuite/synth: add a test for #2090Tristan Gingold2022-06-122-0/+70
* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
* testsuite/synth: add a test for #2089Tristan Gingold2022-06-122-0/+49
* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-127-387/+452
* testsuite/synth: add tests for #2088Tristan Gingold2022-06-114-0/+117
* elab-vhdl_types(Synth_Array_Attribute): handle dimension parameterTristan Gingold2022-06-111-1/+3
* testsuite/synth: add a test for #2086Tristan Gingold2022-06-112-0/+35
* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
* netlists-memories: handle negation for In_Conjunction. Fix #2086Tristan Gingold2022-06-111-8/+3
* synth-vhdl_eval: add support for more operationsTristan Gingold2022-06-111-1/+10
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-119-217/+251
* Merge pull request #2087 from Guiltybyte/support-non-glibctgingold2022-06-091-1/+1
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| * deleted pragma messagesGuiltybyte2022-06-091-2/+0
| * Only enable backtrace on linux if glibc is presentGuiltybyte2022-06-091-1/+3
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* testsuite/synth: add a test for #2085Tristan Gingold2022-06-092-0/+35
* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-097-30/+64
* testsuite/synth: add a test for #2084Tristan Gingold2022-06-092-0/+23
* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-093-5/+16
* testsuite/synth: add a test for #2083Tristan Gingold2022-06-082-0/+39
* synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
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