aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* synth: handle read length on text filesTristan Gingold2022-09-171-16/+40
|
* synth: handle incomplete typesTristan Gingold2022-09-176-24/+87
|
* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
|
* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
|
* synth: preliminary work to factorize codeTristan Gingold2022-09-166-52/+69
|
* simul: handle active attributeTristan Gingold2022-09-164-11/+58
|
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
|
* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
|
* simul: improve error handling during elaborationTristan Gingold2022-09-162-5/+6
|
* synth: improve handling of complex typesTristan Gingold2022-09-154-8/+30
|
* synth: handle vhdl-87 filesTristan Gingold2022-09-152-2/+14
|
* synth: handle access subtypesTristan Gingold2022-09-152-1/+9
|
* synth: handle read for files of unconstrained arraysTristan Gingold2022-09-153-1/+54
|
* simul: handle more signals typesTristan Gingold2022-09-152-23/+128
|
* testsuite/gna: add a test for #2189Tristan Gingold2022-09-154-0/+69
|
* trans-chap7: fix choice of exp. Fix #2189Tristan Gingold2022-09-151-3/+3
|
* ortho/mcode: add reg move for ret. Fix #2189Tristan Gingold2022-09-152-7/+17
|
* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
|
* simul: handle --expect-failure for elaborationTristan Gingold2022-09-143-11/+15
|
* synth: detect overflow in static exponentiationTristan Gingold2022-09-146-76/+266
| | | | src/grt: extract grt.arith from grt.lib
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
|
* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
|
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-123-1/+9
|
* testsuite/synth: add tests for succ/pred/leftof/rightof attributesTristan Gingold2022-09-129-0/+113
|
* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
|
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-117-20/+58
|
* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
|
* simul: move assertions (not to trigger in case of errors)Tristan Gingold2022-09-111-3/+3
|
* simul: optimize resolution call only for std_logicTristan Gingold2022-09-111-5/+11
|
* synth: fix and add checks for memory management.Tristan Gingold2022-09-1016-116/+362
|
* testsuite/synth: add a test with uninitialized shared variableTristan Gingold2022-09-083-1/+101
|
* simul: add support for protected objectsTristan Gingold2022-09-0812-23/+267
|
* testsuite/synth: add a test for #2187Tristan Gingold2022-09-085-0/+410
|
* elab-vhdl_objtypes: handle bounded array base type. Fix #2187Tristan Gingold2022-09-081-1/+2
|
* elab-vhdl_values: factorize codeTristan Gingold2022-09-076-29/+16
|
* simul: do not propagate errors from resolution functionTristan Gingold2022-09-071-0/+3
|
* synth-vhdl_stmts: fix handling of copyback parametersTristan Gingold2022-09-073-26/+38
|
* elab-vhdl_stmts: fix a TODOTristan Gingold2022-09-071-1/+3
|
* synth: handle open entity aspectTristan Gingold2022-09-071-4/+4
|
* elab-vhdl_heap: fix handling of simple access typesTristan Gingold2022-09-071-4/+17
|
* simul: fix computation for number of driversTristan Gingold2022-09-061-1/+2
|
* synth: handle generics in blocksTristan Gingold2022-09-064-10/+53
|
* simul: add an hook to display report/assert messageTristan Gingold2022-09-063-50/+128
|
* synth-vhdl_eval: handle std_logic_signed and std_logic_unsignedTristan Gingold2022-09-061-55/+111
|
* synth: add evaluation for ieee.std_logic_arithTristan Gingold2022-09-056-43/+1181
|
* testsuite/gna: add a test for #2185Tristan Gingold2022-09-028-0/+969
|
* grt: add a SIGFPE handler for linux x86/64. Fix #2185Tristan Gingold2022-09-021-0/+4
|
* synth: extract synth-ieee-utils from synth-ieee-numeric_stdTristan Gingold2022-09-022-21/+46
|
* testsuite/synth: improve test #1460Tristan Gingold2022-09-022-0/+18
|
* synth: improve debug subprogramsTristan Gingold2022-09-022-1/+8
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-16 23:54:05 +0000