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-rw-r--r--testsuite/gna/issue106/case1.vhdl29
-rwxr-xr-xtestsuite/gna/issue106/testsuite.sh3
2 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/gna/issue106/case1.vhdl b/testsuite/gna/issue106/case1.vhdl
new file mode 100644
index 000000000..082612807
--- /dev/null
+++ b/testsuite/gna/issue106/case1.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end entity ent;
+
+architecture arch of ent is
+ signal test: natural;
+ constant e : natural := 3;
+begin
+ LL: case e generate
+ when 0 =>
+ when 1 to 4 =>
+ test <= 1;
+ when l5: 5 | 7=>
+ test <= 2;
+ when others =>
+ end generate ll;
+
+ process
+ begin
+ wait for 0 ns;
+ assert test = 2;
+ wait;
+ end process;
+end architecture arch;
+
+
diff --git a/testsuite/gna/issue106/testsuite.sh b/testsuite/gna/issue106/testsuite.sh
index 011b30fc0..c01c6cf35 100755
--- a/testsuite/gna/issue106/testsuite.sh
+++ b/testsuite/gna/issue106/testsuite.sh
@@ -12,6 +12,9 @@ elab_simulate ent
analyze ent2.vhdl
elab_simulate ent
+analyze case1.vhdl
+elab_simulate ent
+
clean
echo "Test successful"