diff options
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/issue1935/bwc.vhdl | 64 | ||||
-rw-r--r-- | testsuite/gna/issue1935/clock.vhdl | 30 | ||||
-rw-r--r-- | testsuite/gna/issue1935/sm_tb.vhdl | 72 | ||||
-rwxr-xr-x | testsuite/gna/issue1935/testsuite.sh | 10 |
4 files changed, 176 insertions, 0 deletions
diff --git a/testsuite/gna/issue1935/bwc.vhdl b/testsuite/gna/issue1935/bwc.vhdl new file mode 100644 index 000000000..86b6d2948 --- /dev/null +++ b/testsuite/gna/issue1935/bwc.vhdl @@ -0,0 +1,64 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bwc is + port + ( + enable, clock, reset : in std_logic; + button_pressed : in std_logic; + open_window, close_window : out std_logic + ); +end bwc; + +architecture behave of bwc is + +-- User defined type +type SM_State is (w_closed, w_open); +signal current_state, next_state: SM_State; + + +begin + -- State memory process + State_memory: process (clock) + begin + if (reset = '0') then current_state <= w_closed; + + elsif (enable = '1' and rising_edge(clock)) then + current_state <= next_state; + + end if; + end process; + + -- Next state logic + Next_state_logic: process (clock) + begin + case (current_state) is + when w_open => if (button_pressed = '1') + then next_state <= w_closed; + else next_state <= w_open; + end if; + + when w_closed =>if (button_pressed = '1') + then next_state <= w_open; + else next_state <= w_closed; + end if; + end case; + end process; + + -- Output logic + Output_logic: process(clock) + begin + case (current_state) is + when w_open => if (button_pressed = '1') + then open_window <= '0'; close_window <= '1'; + else open_window <= '0'; close_window <= '0'; + end if; + + when w_closed =>if (button_pressed = '1') + then open_window <= '1'; close_window <= '0'; + else open_window <= '0'; close_window <= '0'; + end if; + when others => open_window <= '0'; close_window <= '0'; + end case; + end process; +end architecture; diff --git a/testsuite/gna/issue1935/clock.vhdl b/testsuite/gna/issue1935/clock.vhdl new file mode 100644 index 000000000..6fe2faef9 --- /dev/null +++ b/testsuite/gna/issue1935/clock.vhdl @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity clock is + port( + interval: in time; + EN : in std_logic; + CLK : out std_logic + ); + +end clock; + +architecture behave of clock is + +begin + + clock : process + begin + loop + exit when EN = '0'; + CLK <= not '1'; + wait for interval; + CLK <= not '0'; + wait for interval; + end loop; + + CLK <= '0'; + wait until EN = '1'; + end process; +end architecture; diff --git a/testsuite/gna/issue1935/sm_tb.vhdl b/testsuite/gna/issue1935/sm_tb.vhdl new file mode 100644 index 000000000..21b7942e1 --- /dev/null +++ b/testsuite/gna/issue1935/sm_tb.vhdl @@ -0,0 +1,72 @@ +library ieee;
+use ieee.std_logic_1164.all;
+
+entity SM_tb is
+end SM_tb;
+
+ architecture test of SM_tb is
+
+ component clock is
+ port(
+ interval: in time;
+ EN : in std_logic;
+ CLK : out std_logic
+ );
+ end component;
+
+ component bwc is
+ port
+ (
+ enable, clock, reset : in std_logic;
+ button_pressed : in std_logic;
+ open_window, close_window : out std_logic;
+ );
+ end component;
+
+ signal enable: std_logic := '0';
+
+ signal CLK0, CLK1, CLK2, CLK3: std_logic;
+ signal CLKenable: std_logic := '0';
+
+ signal o1, o2: std_logic;
+
+
+ begin
+ clk_0 : clock port map (CLK => CLK0, interval => 0.5 ns, EN=> CLKenable);
+ clk_1 : clock port map (CLK => CLK1, interval => 1 ns, EN=> CLKenable);
+ clk_2 : clock port map (CLK => CLK2, interval => 2 ns, EN=> CLKenable);
+ clk_3 : clock port map (CLK => CLK3, interval => 4 ns, EN=> CLKenable);
+
+ sm_entity : bwc port map (enable => enable, clock => clk0, reset => '1', button_pressed => CLK1, open_window => o1, close_window => o2)
+ -- enable <= '0';
+ -- b <= '0';
+
+ process begin
+ wait for 1 ns;
+ CLKenable <= '1';
+ wait for 1 ns;
+ enable <= '1';
+ wait for 10 ns;
+
+ -- b <= '1';
+
+ -- a <= 'X';
+ -- b <= 'X';
+ -- wait for 10 ns;
+
+
+ -- enable <= '0';
+ -- b <= '0';
+ -- wait for 10 ns;
+
+ -- b <= '1';
+ -- wait for 1 ns;
+
+
+
+ assert false report "Test is done.";
+ wait;
+
+ end process;
+
+ end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue1935/testsuite.sh b/testsuite/gna/issue1935/testsuite.sh new file mode 100755 index 000000000..938cb95c5 --- /dev/null +++ b/testsuite/gna/issue1935/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze clock.vhdl bwc.vhdl +analyze_failure sm_tb.vhdl + +clean + +echo "Test successful" |