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-rw-r--r--testsuite/gna/issue376/fx3_model_modified.vhdl215
-rw-r--r--testsuite/gna/issue376/fx3_model_unmodified.vhdl193
-rw-r--r--testsuite/gna/issue376/repro.vhdl25
-rw-r--r--testsuite/gna/issue376/repro2.vhdl12
-rw-r--r--testsuite/gna/issue376/repro_pkg.vhdl0
-rwxr-xr-xtestsuite/gna/issue376/testsuite.sh19
-rw-r--r--testsuite/gna/issue376/util.vhdl191
7 files changed, 655 insertions, 0 deletions
diff --git a/testsuite/gna/issue376/fx3_model_modified.vhdl b/testsuite/gna/issue376/fx3_model_modified.vhdl
new file mode 100644
index 000000000..204024cda
--- /dev/null
+++ b/testsuite/gna/issue376/fx3_model_modified.vhdl
@@ -0,0 +1,215 @@
+-- Copyright (c) 2013 Nuand LLC
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+
+library ieee ;
+ use ieee.std_logic_1164.all ;
+ use ieee.numeric_std.all ;
+ use ieee.math_real.all ;
+ use ieee.math_complex.all ;
+
+library nuand ;
+ use nuand.util.all ;
+
+entity fx3_model is
+ port (
+ fx3_pclk : buffer std_logic := '1' ;
+ fx3_gpif : inout std_logic_vector(31 downto 0) ;
+ fx3_ctl : inout std_logic_vector(12 downto 0) ;
+ fx3_uart_rxd : in std_logic ;
+ fx3_uart_txd : buffer std_logic ;
+ fx3_uart_cts : buffer std_logic ;
+ fx3_rx_en : in std_logic ;
+ fx3_rx_meta_en : in std_logic ;
+ fx3_tx_en : in std_logic ;
+ fx3_tx_meta_en : in std_logic
+ ) ;
+end entity ; -- fx3_model
+
+architecture dma of fx3_model is
+
+ constant PCLK_HALF_PERIOD : time := 1 sec * (1.0/100.0e6/2.0) ;
+
+ -- Control mapping
+ -- alias dma0_rx_ack is fx3_ctl( 0) ;
+ -- alias dma1_rx_ack is fx3_ctl( 1) ;
+ -- alias dma2_tx_ack is fx3_ctl( 2) ;
+ -- alias dma3_tx_ack is fx3_ctl( 3) ;
+ -- alias dma_rx_enable is fx3_ctl( 4) ;
+ -- alias dma_tx_enable is fx3_ctl( 5) ;
+ -- alias dma_idle is fx3_ctl( 6) ;
+ -- alias system_reset is fx3_ctl( 7) ;
+ -- alias dma0_rx_reqx is fx3_ctl( 8) ;
+ -- alias dma1_rx_reqx is fx3_ctl(12) ; -- due to 9 being connected to dclk
+ -- alias dma2_tx_reqx is fx3_ctl(10) ;
+ -- alias dma3_tx_reqx is fx3_ctl(11) ;
+
+ type gpif_state_t is (IDLE, TX_SAMPLES, RX_SAMPLES) ;
+ signal gpif_state : gpif_state_t ;
+
+begin
+
+ -- DCLK which isn't used
+ fx3_ctl(9) <= '0' ;
+
+ -- Create a 100MHz clock output
+ fx3_pclk <= not fx3_pclk after PCLK_HALF_PERIOD ;
+
+ rx_sample_stream : process
+ constant BLOCK_SIZE : natural := 512 ;
+ variable count : natural := 0 ;
+ begin
+ -- dma0_rx_reqx <= '1' ;
+ fx3_ctl (8) <= '1' ;
+ -- dma1_rx_reqx <= '1' ;
+ fx3_ctl (12) <= '1' ;
+ -- dma_rx_enable <= '0' ;
+ fx3_ctl (4) <= '0' ;
+ -- wait until rising_edge(fx3_pclk) and system_reset = '0' ;
+ wait until rising_edge(fx3_pclk) and fx3_ctl (7) = '0' ;
+ for i in 1 to 10 loop
+ wait until rising_edge( fx3_pclk ) ;
+ end loop ;
+ if( fx3_rx_en = '0' ) then
+ wait;
+ end if;
+ wait for 30 us;
+ -- dma_rx_enable <= '1' ;
+ fx3_ctl (4) <= '1' ;
+ while true loop
+ for i in 0 to 2 loop
+ -- dma0_rx_reqx <= '0' ;
+ fx3_ctl (8) <= '0' ;
+ -- wait until rising_edge( fx3_pclk ) and dma0_rx_ack = '1' ;
+ wait until rising_edge( fx3_pclk ) and fx3_ctl (0) = '1' ;
+ wait until rising_edge( fx3_pclk ) ;
+ wait until rising_edge( fx3_pclk ) ;
+ -- dma0_rx_reqx <= '1' ;
+ fx3_ctl (8) <= '1' ;
+ for i in 1 to BLOCK_SIZE loop
+ wait until rising_edge( fx3_pclk ) ;
+ end loop ;
+ end loop ;
+ -- dma_rx_enable <= '0' ;
+ fx3_ctl (4) <= '0' ;
+ for i in 0 to 5000 loop
+ wait until rising_edge(fx3_pclk) ;
+ end loop ;
+ -- dma_rx_enable <= '1' ;
+ fx3_ctl (4) <= '1' ;
+ for i in 0 to 10 loop
+ wait until rising_edge(fx3_pclk);
+ end loop ;
+ end loop ;
+ report "Done with RX sample stream" ;
+ wait ;
+ end process ;
+
+ tx_sample_stream : process
+ constant BLOCK_SIZE : natural := 512 ;
+ variable count : natural := 0 ;
+ variable timestamp_cntr : natural := 80;
+ variable header_len : natural := 0;
+ begin
+ -- dma2_tx_reqx <= '1' ;
+ fx3_ctl (10) <= '1' ;
+ -- dma3_tx_reqx <= '1' ;
+ fx3_ctl (11) <= '1' ;
+ -- dma_tx_enable <= '0' ;
+ fx3_ctl (5) <= '0' ;
+ fx3_gpif <= (others =>'Z') ;
+ -- wait until system_reset = '0' ;
+ wait until fx3_ctl (7) = '0' ;
+ for i in 0 to 1000 loop
+ wait until rising_edge( fx3_pclk ) ;
+ end loop ;
+ if( fx3_tx_en = '0' ) then
+ wait;
+ end if;
+ wait for 120 us;
+ -- dma_tx_enable <= '1' ;
+ fx3_ctl (5) <= '1' ;
+ for i in 0 to 3 loop
+ -- dma3_tx_reqx <= '0' ;
+ fx3_ctl (11) <= '0' ;
+ -- wait until rising_edge( fx3_pclk ) and dma3_tx_ack = '1' ;
+ wait until rising_edge( fx3_pclk ) and fx3_ctl (3) = '1' ;
+ wait until rising_edge( fx3_pclk ) ;
+ wait until rising_edge( fx3_pclk ) ;
+ -- dma3_tx_reqx <= '1' ;
+ fx3_ctl (11) <= '1' ;
+ if( fx3_tx_meta_en = '1') then
+ for i in 1 to 4 loop
+ if (i = 1 ) then
+ fx3_gpif <= x"12341234";
+ elsif (i = 3 ) then
+ fx3_gpif <= (others => '0');
+ elsif(i = 4) then
+ fx3_gpif <= (others => '1');
+ elsif (i = 2) then
+ fx3_gpif(31 downto 0) <= std_logic_vector(to_signed(timestamp_cntr, 32));
+ timestamp_cntr := timestamp_cntr + 508 * 2;
+ end if;
+ wait until rising_edge( fx3_pclk );
+ end loop;
+ header_len := 4;
+ else
+ header_len := 0;
+ end if;
+ for i in 1 to BLOCK_SIZE - header_len loop
+ fx3_gpif(31 downto 16) <= std_logic_vector(to_signed(count, 16)) ;
+ fx3_gpif(15 downto 0) <= std_logic_vector(to_signed(-count, 16)) ;
+ count := (count + 1) mod 2048 ;
+ wait until rising_edge( fx3_pclk );
+ end loop ;
+ fx3_gpif <= (others =>'Z');
+ for i in 1 to 10 loop
+ wait until rising_edge( fx3_pclk );
+ end loop ;
+ end loop ;
+ report "Done with TX sample stream" ;
+ wait ;
+ end process ;
+
+ reset_system : process
+ begin
+ -- system_reset <= '1' ;
+ fx3_ctl (7) <= '1' ;
+ -- dma_idle <= '0' ;
+ fx3_ctl (6) <= '0' ;
+ nop( fx3_pclk, 100 ) ;
+ -- system_reset <= '0' ;
+ fx3_ctl (7) <= '0' ;
+ nop( fx3_pclk, 10 ) ;
+ -- dma_idle <= '1' ;
+ fx3_ctl (6) <= '1' ;
+ wait ;
+ end process ;
+
+ -- TODO: UART Interface
+ fx3_uart_txd <= '1' ;
+ fx3_uart_cts <= '1' ;
+
+end architecture ; -- dma
+
+architecture inband_scheduler of fx3_model is
+
+begin
+
+end architecture ; -- inband_scheduler
diff --git a/testsuite/gna/issue376/fx3_model_unmodified.vhdl b/testsuite/gna/issue376/fx3_model_unmodified.vhdl
new file mode 100644
index 000000000..7ad45fc5e
--- /dev/null
+++ b/testsuite/gna/issue376/fx3_model_unmodified.vhdl
@@ -0,0 +1,193 @@
+-- Copyright (c) 2013 Nuand LLC
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+
+library ieee ;
+ use ieee.std_logic_1164.all ;
+ use ieee.numeric_std.all ;
+ use ieee.math_real.all ;
+ use ieee.math_complex.all ;
+
+library nuand ;
+ use nuand.util.all ;
+
+entity fx3_model is
+ port (
+ fx3_pclk : buffer std_logic := '1' ;
+ fx3_gpif : inout std_logic_vector(31 downto 0) ;
+ fx3_ctl : inout std_logic_vector(12 downto 0) ;
+ fx3_uart_rxd : in std_logic ;
+ fx3_uart_txd : buffer std_logic ;
+ fx3_uart_cts : buffer std_logic ;
+ fx3_rx_en : in std_logic ;
+ fx3_rx_meta_en : in std_logic ;
+ fx3_tx_en : in std_logic ;
+ fx3_tx_meta_en : in std_logic
+ ) ;
+end entity ; -- fx3_model
+
+architecture dma of fx3_model is
+
+ constant PCLK_HALF_PERIOD : time := 1 sec * (1.0/100.0e6/2.0) ;
+
+ -- Control mapping
+ alias dma0_rx_ack is fx3_ctl( 0) ;
+ alias dma1_rx_ack is fx3_ctl( 1) ;
+ alias dma2_tx_ack is fx3_ctl( 2) ;
+ alias dma3_tx_ack is fx3_ctl( 3) ;
+ alias dma_rx_enable is fx3_ctl( 4) ;
+ alias dma_tx_enable is fx3_ctl( 5) ;
+ alias dma_idle is fx3_ctl( 6) ;
+ alias system_reset is fx3_ctl( 7) ;
+ alias dma0_rx_reqx is fx3_ctl( 8) ;
+ alias dma1_rx_reqx is fx3_ctl(12) ; -- due to 9 being connected to dclk
+ alias dma2_tx_reqx is fx3_ctl(10) ;
+ alias dma3_tx_reqx is fx3_ctl(11) ;
+
+ type gpif_state_t is (IDLE, TX_SAMPLES, RX_SAMPLES) ;
+ signal gpif_state : gpif_state_t ;
+
+begin
+
+ -- DCLK which isn't used
+ fx3_ctl(9) <= '0' ;
+
+ -- Create a 100MHz clock output
+ fx3_pclk <= not fx3_pclk after PCLK_HALF_PERIOD ;
+
+ rx_sample_stream : process
+ constant BLOCK_SIZE : natural := 512 ;
+ variable count : natural := 0 ;
+ begin
+ dma0_rx_reqx <= '1' ;
+ dma1_rx_reqx <= '1' ;
+ dma_rx_enable <= '0' ;
+ wait until rising_edge(fx3_pclk) and system_reset = '0' ;
+ for i in 1 to 10 loop
+ wait until rising_edge( fx3_pclk ) ;
+ end loop ;
+ if( fx3_rx_en = '0' ) then
+ wait;
+ end if;
+ wait for 30 us;
+ dma_rx_enable <= '1' ;
+ while true loop
+ for i in 0 to 2 loop
+ dma0_rx_reqx <= '0' ;
+ wait until rising_edge( fx3_pclk ) and dma0_rx_ack = '1' ;
+ wait until rising_edge( fx3_pclk ) ;
+ wait until rising_edge( fx3_pclk ) ;
+ dma0_rx_reqx <= '1' ;
+ for i in 1 to BLOCK_SIZE loop
+ wait until rising_edge( fx3_pclk ) ;
+ end loop ;
+ end loop ;
+ dma_rx_enable <= '0' ;
+ for i in 0 to 5000 loop
+ wait until rising_edge(fx3_pclk) ;
+ end loop ;
+ dma_rx_enable <= '1' ;
+ for i in 0 to 10 loop
+ wait until rising_edge(fx3_pclk);
+ end loop ;
+ end loop ;
+ report "Done with RX sample stream" ;
+ wait ;
+ end process ;
+
+ tx_sample_stream : process
+ constant BLOCK_SIZE : natural := 512 ;
+ variable count : natural := 0 ;
+ variable timestamp_cntr : natural := 80;
+ variable header_len : natural := 0;
+ begin
+ dma2_tx_reqx <= '1' ;
+ dma3_tx_reqx <= '1' ;
+ dma_tx_enable <= '0' ;
+ fx3_gpif <= (others =>'Z') ;
+ wait until system_reset = '0' ;
+ for i in 0 to 1000 loop
+ wait until rising_edge( fx3_pclk ) ;
+ end loop ;
+ if( fx3_tx_en = '0' ) then
+ wait;
+ end if;
+ wait for 120 us;
+ dma_tx_enable <= '1' ;
+ for i in 0 to 3 loop
+ dma3_tx_reqx <= '0' ;
+ wait until rising_edge( fx3_pclk ) and dma3_tx_ack = '1' ;
+ wait until rising_edge( fx3_pclk ) ;
+ wait until rising_edge( fx3_pclk ) ;
+ dma3_tx_reqx <= '1' ;
+ if( fx3_tx_meta_en = '1') then
+ for i in 1 to 4 loop
+ if (i = 1 ) then
+ fx3_gpif <= x"12341234";
+ elsif (i = 3 ) then
+ fx3_gpif <= (others => '0');
+ elsif(i = 4) then
+ fx3_gpif <= (others => '1');
+ elsif (i = 2) then
+ fx3_gpif(31 downto 0) <= std_logic_vector(to_signed(timestamp_cntr, 32));
+ timestamp_cntr := timestamp_cntr + 508 * 2;
+ end if;
+ wait until rising_edge( fx3_pclk );
+ end loop;
+ header_len := 4;
+ else
+ header_len := 0;
+ end if;
+ for i in 1 to BLOCK_SIZE - header_len loop
+ fx3_gpif(31 downto 16) <= std_logic_vector(to_signed(count, 16)) ;
+ fx3_gpif(15 downto 0) <= std_logic_vector(to_signed(-count, 16)) ;
+ count := (count + 1) mod 2048 ;
+ wait until rising_edge( fx3_pclk );
+ end loop ;
+ fx3_gpif <= (others =>'Z');
+ for i in 1 to 10 loop
+ wait until rising_edge( fx3_pclk );
+ end loop ;
+ end loop ;
+ report "Done with TX sample stream" ;
+ wait ;
+ end process ;
+
+ reset_system : process
+ begin
+ system_reset <= '1' ;
+ dma_idle <= '0' ;
+ nop( fx3_pclk, 100 ) ;
+ system_reset <= '0' ;
+ nop( fx3_pclk, 10 ) ;
+ dma_idle <= '1' ;
+ wait ;
+ end process ;
+
+ -- TODO: UART Interface
+ fx3_uart_txd <= '1' ;
+ fx3_uart_cts <= '1' ;
+
+end architecture ; -- dma
+
+architecture inband_scheduler of fx3_model is
+
+begin
+
+end architecture ; -- inband_scheduler
diff --git a/testsuite/gna/issue376/repro.vhdl b/testsuite/gna/issue376/repro.vhdl
new file mode 100644
index 000000000..6c15650df
--- /dev/null
+++ b/testsuite/gna/issue376/repro.vhdl
@@ -0,0 +1,25 @@
+package pkg is
+ type enum is ('a', 'b', 'c');
+ type enum_vec is array (natural range <>) of enum;
+ function resolved (v : enum_vec) return enum;
+ subtype res_enum is (resolved) enum_vec;
+end pkg;
+
+package body pkg is
+ function resolved (v : enum_vec) return enum is
+ begin
+ return v (v'left);
+ end resolved;
+end;
+
+use work.pkg.all;
+
+entity repro is
+ port (p : inout res_enum (3 downto 0));
+end repro;
+
+architecture behav of repro is
+ alias p_0 is p(0);
+begin
+ p_0 <= 'a' after 1 ns, 'b' after 4 ns;
+end behav;
diff --git a/testsuite/gna/issue376/repro2.vhdl b/testsuite/gna/issue376/repro2.vhdl
new file mode 100644
index 000000000..d4807195d
--- /dev/null
+++ b/testsuite/gna/issue376/repro2.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+ port (p : inout std_logic_vector (3 downto 0));
+end repro2;
+
+architecture behav of repro2 is
+ alias p_0 is p(0);
+begin
+ p_0 <= '0' after 1 ns, '1' after 4 ns;
+end behav;
diff --git a/testsuite/gna/issue376/repro_pkg.vhdl b/testsuite/gna/issue376/repro_pkg.vhdl
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/testsuite/gna/issue376/repro_pkg.vhdl
diff --git a/testsuite/gna/issue376/testsuite.sh b/testsuite/gna/issue376/testsuite.sh
new file mode 100755
index 000000000..4a7a753c4
--- /dev/null
+++ b/testsuite/gna/issue376/testsuite.sh
@@ -0,0 +1,19 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate repro
+
+analyze repro2.vhdl
+elab_simulate repro2
+
+analyze --work=nuand util.vhdl
+analyze fx3_model_unmodified.vhdl
+elab_simulate fx3_model
+
+clean nuand
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue376/util.vhdl b/testsuite/gna/issue376/util.vhdl
new file mode 100644
index 000000000..94100ce8f
--- /dev/null
+++ b/testsuite/gna/issue376/util.vhdl
@@ -0,0 +1,191 @@
+library ieee ;
+ use ieee.std_logic_1164.all ;
+
+library std;
+ use std.textio.all;
+
+
+-- Utility package
+package util is
+
+ procedure nop( signal clock : in std_logic ; count : in natural ) ;
+
+end package ;
+
+package body util is
+
+ procedure nop( signal clock : in std_logic ; count : in natural ) is
+ begin
+ for i in 1 to count loop
+ wait until rising_edge( clock ) ;
+ end loop ;
+ end procedure ;
+
+end package body ;
+
+library ieee ;
+ use ieee.std_logic_1164.all ;
+ use ieee.numeric_std.all;
+library std;
+ use std.textio.all;
+
+
+entity data_saver is
+ generic(
+ FILENAME : string := "file.dat";
+ DATA_WIDTH : natural := 16
+ );
+ port(
+ reset : in std_logic;
+ clock : in std_logic;
+ data : std_logic_vector(DATA_WIDTH-1 downto 0);
+ data_valid : std_logic
+ );
+end entity;
+
+
+architecture arch of data_saver is
+begin
+
+ handler : process
+ FILE fp : text;
+ variable line_data : line;
+ begin
+ --
+ wait until falling_edge(reset);
+
+ file_open(fp, FILENAME, WRITE_MODE);
+
+ while (reset = '0') loop
+ wait until rising_edge(data_valid);
+ write(line_data, data);
+ writeline(fp,line_data);
+ end loop;
+ file_close(fp);
+ end process;
+end architecture;
+
+
+library ieee ;
+ use ieee.std_logic_1164.all ;
+ use ieee.numeric_std.all;
+library std;
+ use std.textio.all;
+
+
+entity signed_saver is
+ generic(
+ FILENAME : string := "file.dat";
+ DATA_WIDTH : natural := 16
+ );
+ port(
+ reset : in std_logic;
+ clock : in std_logic;
+ data : signed(DATA_WIDTH-1 downto 0);
+ data_valid : std_logic
+ );
+end entity;
+
+
+architecture arch of signed_saver is
+begin
+
+ handler : process
+ FILE fp : text;
+ variable line_data : line;
+ begin
+ --
+ wait until falling_edge(reset);
+
+ file_open(fp, FILENAME, WRITE_MODE);
+
+ while (reset = '0') loop
+ wait until rising_edge(clock);
+
+ if data_valid = '1' then
+ write(line_data, (to_integer(data)));
+ writeline(fp,line_data);
+ end if;
+ end loop;
+ file_close(fp);
+ end process;
+end architecture;
+
+
+
+library ieee ;
+ use ieee.std_logic_1164.all ;
+ use ieee.numeric_std.all;
+library std;
+ use std.textio.all;
+
+
+entity data_reader is
+ generic(
+ FILENAME : string := "file.dat";
+ DATA_WIDTH : natural := 16
+ );
+ port(
+ reset : in std_logic;
+ clock : in std_logic;
+ data_request : in std_logic;
+ data : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ data_valid : out std_logic
+ );
+end entity;
+
+
+architecture arch of data_reader is
+
+ type character_array_t is array (natural range <>) of character;
+begin
+
+ handler : process
+ variable line_data : line;
+ variable tmp : integer;
+ variable c : character;--_array_t(0 to 3);
+
+ type bin_t is file of character ;
+ file fp : bin_t ;
+ variable fs : file_open_status ;
+ begin
+ --
+ data <= (others => '0');
+ data_valid <= '0';
+ wait until falling_edge(reset);
+
+ file_open(fs, fp, FILENAME, READ_MODE);
+
+ if( fs /= OPEN_OK ) then
+ report "File open issues" severity failure ;
+ end if ;
+
+ --readline(fp,line_data);
+ while (reset = '0') loop
+
+ wait until rising_edge(clock);
+ data_valid <= '0';
+
+ if data_request = '1' then
+ read(fp, c);
+ tmp := integer(natural(character'pos(c)));
+ data(7 downto 0) <= std_logic_vector(to_unsigned(tmp,8));
+ read(fp, c);
+ tmp := integer(natural(character'pos(c)));
+ data(15 downto 8) <= std_logic_vector(to_unsigned(tmp,8));
+ read(fp, c);
+ tmp := integer(natural(character'pos(c)));
+ data(23 downto 16) <= std_logic_vector(to_unsigned(tmp,8));
+ read(fp, c);
+ tmp := integer(natural(character'pos(c)));
+ data(31 downto 24) <= std_logic_vector(to_unsigned(tmp,8));
+
+ data_valid <= '1';
+ wait until rising_edge(clock);
+ data_valid <= '0';
+ end if;
+
+ end loop;
+ file_close(fp);
+ end process;
+end architecture;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 22:08:35 +0000