3 files changed, 80 insertions, 0 deletions
diff --git a/testsuite/gna/issue2337/repro2_tb.vhdl b/testsuite/gna/issue2337/repro2_tb.vhdl
new file mode 100644
index 000000000..d2af7d4a8
--- /dev/null
+++ b/testsuite/gna/issue2337/repro2_tb.vhdl
@@ -0,0 +1,30 @@
+entity repro2_tb is
+end entity repro2_tb;
+
+architecture sim of repro2_tb is
+    type Test_Record_t is record
+        test     : bit_vector(8 downto 0);
+        expected  : bit_vector(8 downto 0);
+    end record;
+
+    type SLV_vector is array (natural range <>) of bit_vector;
+
+    -- Want to create an array of test values without explicitely stating the size
+    -- The following line breaks GHDL, if I replace "open" with "0 to 1" everything works as expected.
+    constant TEST_VALUES : SLV_vector(open)(7 downto 0) := (
+        x"AD",
+        x"12"
+    );
+
+    constant TEST_VEC : Test_Record_t := (
+        test      => "0" & TEST_VALUES(0), -- The concatenation is somehow necessary to reproduce the issue
+        expected  => "0" & TEST_VALUES(0)
+    );
+begin
+    test_runner : process
+    begin
+        assert TEST_VEC.test = TEST_VEC.expected report "Should be equal" severity failure;
+        wait;
+    end process test_runner;
+
+end architecture sim;
diff --git a/testsuite/gna/issue2337/repro_tb.vhdl b/testsuite/gna/issue2337/repro_tb.vhdl
new file mode 100644
index 000000000..a8dde9daf
--- /dev/null
+++ b/testsuite/gna/issue2337/repro_tb.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.env.finish;
+
+entity repro_tb is
+end entity repro_tb;
+
+architecture sim of repro_tb is
+    type Test_Record_t is record
+        test     : std_logic_vector(8 downto 0);
+        expected  : std_logic_vector(8 downto 0);
+    end record;
+
+    type SLV_vector is array (natural range <>) of std_logic_vector;
+
+    -- Want to create an array of test values without explicitely stating the size
+    -- The following line breaks GHDL, if I replace "open" with "0 to 1" everything works as expected.
+    constant TEST_VALUES : SLV_vector(open)(7 downto 0) := (
+        x"AD",
+        x"12"
+    );
+
+    constant TEST_VEC : Test_Record_t := (
+        test      => "0" & TEST_VALUES(0), -- The concatenation is somehow necessary to reproduce the issue
+        expected  => "0" & TEST_VALUES(0)
+    );
+begin
+    test_runner : process
+    begin
+        assert TEST_VEC.test = TEST_VEC.expected report "Should be equal" severity failure;
+        finish;
+    end process test_runner;
+
+end architecture sim;
diff --git a/testsuite/gna/issue2337/testsuite.sh b/testsuite/gna/issue2337/testsuite.sh
new file mode 100755
index 000000000..a625378ce
--- /dev/null
+++ b/testsuite/gna/issue2337/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro_tb.vhdl
+elab_simulate repro_tb
+
+analyze repro2_tb.vhdl
+elab_simulate repro2_tb
+
+clean
+
+echo "Test successful"