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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/resolution')
15 files changed, 989 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd new file mode 100644 index 000000000..82c582609 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package MVL4 is + + type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type + + type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic; + + function resolve_MVL4 ( contribution : MVL4_ulogic_vector ) + return MVL4_ulogic; + + subtype MVL4_logic is resolve_MVL4 MVL4_ulogic; + + -- code from book (in text) + + type MVL4_logic_vector is array (natural range <>) of MVL4_logic; + + -- end code from book + +end package MVL4; + +-------------------------------------------------- + +package body MVL4 is + + type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic; + + constant resolution_table : table := + -- 'X' '0' '1' 'Z' + -- ------------------ + ( ( 'X', 'X', 'X', 'X' ), -- 'X' + ( 'X', '0', 'X', '0' ), -- '0' + ( 'X', 'X', '1', '1' ), -- '1' + ( 'X', '0', '1', 'Z' ) ); -- 'Z' + + function resolve_MVL4 ( contribution : MVL4_ulogic_vector ) + return MVL4_ulogic is + variable result : MVL4_ulogic := 'Z'; + begin + for index in contribution'range loop + result := resolution_table(result, contribution(index)); + end loop; + return result; + end function resolve_MVL4; + +end package body MVL4; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd new file mode 100644 index 000000000..8efe10e6a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd @@ -0,0 +1,92 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity bus_module is + port ( synch : inout std_ulogic; -- . . . ); + -- not in book + other_port : in std_ulogic := 'U' ); + -- end not in book +end entity bus_module; + +-------------------------------------------------- + +-- not in book + + + +library ieee; use ieee.std_logic_1164.all; + +entity bus_based_system is +end entity bus_based_system; + +-- end not in book + + +architecture top_level of bus_based_system is + + signal synch_control : std_logic; + -- . . . + +begin + + synch_control_pull_up : synch_control <= 'H'; + + bus_module_1 : entity work.bus_module(behavioral) + port map ( synch => synch_control, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + bus_module_2 : entity work.bus_module(behavioral) + port map ( synch => synch_control, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + -- . . . + +end architecture top_level; + + + +architecture behavioral of bus_module is +begin + + behavior : process is + -- . . . + -- not in book + constant Tdelay_synch : delay_length := 10 ns; + constant wait_delay : delay_length := 100 ns; + -- end not in book + begin + synch <= '0' after Tdelay_synch; + -- . . . + -- not in book + wait for wait_delay; + -- end not in book + -- ready to start operation + synch <= 'Z' after Tdelay_synch; + wait until synch = 'H'; + -- proceed with operation + -- . . . + end process behavior; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd new file mode 100644 index 000000000..6bd829c2f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd @@ -0,0 +1,118 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +use work.words.all; + +entity cpu is + port ( address : out uword; data : inout uword; -- . . . ); + -- not in book + other_port : in X01Z := 'Z' ); + -- end not in book +end entity cpu; + + +-- not in book + +architecture behavioral of cpu is +begin +end architecture behavioral; + +-- end not in book + + +-------------------------------------------------- + +use work.words.all; + +entity memory is + port ( address : in uword; data : inout uword; -- . . . ); + -- not in book + other_port : in X01Z := 'Z' ); + -- end not in book +end entity memory; + + +-- not in book + +architecture behavioral of memory is +begin +end architecture behavioral; + +-- end not in book + + +-------------------------------------------------- + + +-- not in book + +use work.words.all; + +entity ROM is + port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' ); +end entity ROM; + + +architecture behavioral of ROM is +begin +end architecture behavioral; + + +entity computer_system is +end entity computer_system; + +-- end not in book + + + +architecture top_level of computer_system is + + use work.words.all; + + signal address : uword; + signal data : word; + -- . . . + +begin + + the_cpu : entity work.cpu(behavioral) + port map ( address, data, -- . . . ); + -- not in book + open ); + -- end not in book + + the_memory : entity work.memory(behavioral) + port map ( address, data, -- . . . ); + -- not in book + open ); + -- end not in book + + -- . . . + + -- code from book (in text) + +-- boot_rom : entity work.ROM(behavioral) +-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal +-- -- not in book +-- other_port => open ); +-- -- end not in book + + -- end code from book + +end architecture top_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt new file mode 100644 index 000000000..433c3104d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt @@ -0,0 +1,30 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 15 - Resolved Signals +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +resolve_tri_state_logic.vhd entity resolve_tri_state_logic test Section 15.1, Figure 15-1 +MVL4.vhd package MVL4 body Section 15.1, Figure 15-2 +tri_state_buffer.vhd entity tri_state_buffer behavioral Figure 15.3 +misc_logic.vhd entity misc_logic gate_level Figure 15.4 +words.vhd package words body Figure 15.5 +computer_system.vhd entity cpu behavioral Figure 15.6 +-- entity memory behavioral Figure 15.6 +-- entity ROM behavioral -- +-- entity computer_system top_level Figure 15.6 +memory_system.vhd entity ROM behavioral Figure 15-7 +-- entity SIMM behavioral Figure 15-7 +-- entity memory_system detailed Figure 15-7 +resolved.vhd package resolved body Figure 15-8 +bus_based_system.vhd entity bus_module behavioral Figures 15-9, 15-10 +-- entity bus_based_system top_level Figure 15-9 +synchronize.vhd package synchronize body Figure 15-12 +synchronized_module.vhd entity synchronized_module test Figure 15-13 +inline_01.vhd entity inline_01 test Section 15.1 +inline_02.vhd package inline_02 test Section 15.2 +inline_03.vhd entity IO_section -- Section 15.3 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd new file mode 100644 index 000000000..84df14af6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd @@ -0,0 +1,76 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_01 is + +end entity inline_01; + + +---------------------------------------------------------------- + + +architecture test of inline_01 is + + type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type + + -- code from book: + + type small_int is range 1 to 4; + type small_array is array (small_int range <>) of -- . . . ; + -- not in book + MVL4_ulogic; + -- end not in book + + -- end of code from book + + type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic; + constant resolution_table : table := + -- 'X' '0' '1' 'Z' + -- ------------------ + ( ( 'X', 'X', 'X', 'X' ), -- 'X' + ( 'X', '0', 'X', '0' ), -- '0' + ( 'X', 'X', '1', '1' ), -- '1' + ( 'X', '0', '1', 'Z' ) ); -- 'Z' + + function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is + variable result : MVL4_ulogic := 'Z'; + begin + for index in contribution'range loop + result := resolution_table(result, contribution(index)); + end loop; + return result; + end function resolve_MVL4; + + subtype MVL4_logic is resolve_MVL4 MVL4_ulogic; + + signal s : MVL4_logic; + +begin + + driver_1 : s <= 'Z'; + + driver_2 : s <= 'Z'; + + driver_3 : s <= 'Z'; + + driver_4 : s <= 'Z'; + + driver_5 : s <= 'Z'; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd new file mode 100644 index 000000000..5c5fb5d9d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd @@ -0,0 +1,52 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_02 is + + -- code from book + + type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); + + type std_ulogic_vector is array ( natural range <> ) of std_ulogic; + + function resolved ( s : std_ulogic_vector ) return std_ulogic; + + subtype std_logic is resolved std_ulogic; + + type std_logic_vector is array ( natural range <>) of std_logic; + + subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1') + subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z') + subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1') + subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z') + + -- end code from book + +end package inline_02; + + + +package body inline_02 is + + function resolved ( s : std_ulogic_vector ) return std_ulogic is + begin + return 'U'; + end function resolved; + +end package body inline_02; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd new file mode 100644 index 000000000..c459a8faa --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd @@ -0,0 +1,27 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity IO_section is + port ( data_ack : inout std_logic; -- . . . ); + -- not in book + other_port : in std_ulogic := 'U' ); + -- end not in book +end entity IO_section; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd new file mode 100644 index 000000000..53f67971d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd @@ -0,0 +1,87 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +use work.MVL4.all; + +entity ROM is + port ( a : in MVL4_ulogic_vector(15 downto 0); + d : inout MVL4_logic_vector(7 downto 0); + rd : in MVL4_ulogic ); +end entity ROM; + +-- not in book +architecture behavioral of ROM is +begin +end architecture behavioral; +-- end not in book + +-------------------------------------------------- + +use work.MVL4.all; + +entity SIMM is + port ( a : in MVL4_ulogic_vector(9 downto 0); + d : inout MVL4_logic_vector(31 downto 0); + ras, cas, we, cs : in MVL4_ulogic ); +end entity SIMM; + +-- not in book +architecture behavioral of SIMM is +begin +end architecture behavioral; +-- end not in book + +-------------------------------------------------- + +-- not in book + +use work.MVL4.all; + +entity memory_subsystem is +end entity memory_subsystem; + +-- end not in book + +architecture detailed of memory_subsystem is + + signal internal_data : MVL4_logic_vector(31 downto 0); + -- . . . + + -- not in book + signal internal_addr : MVL4_ulogic_vector(31 downto 0); + signal main_mem_addr : MVL4_ulogic_vector(9 downto 0); + signal ROM_select : MVL4_ulogic; + -- end not in book + +begin + + boot_ROM : entity work.ROM(behavioral) + port map ( a => internal_addr(15 downto 0), + d => internal_data(7 downto 0), + rd => ROM_select ); + + main_mem : entity work.SIMM(behavioral) + port map ( a => main_mem_addr, d => internal_data, -- . . . ); + -- not in book + ras => '0', cas => '0', we => '0', cs => '0' ); + -- end not in book + + -- . . . + +end architecture detailed; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd new file mode 100644 index 000000000..34b6f84fa --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd @@ -0,0 +1,73 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity misc_logic is +end entity misc_logic; + +-- end not in book + + + +use work.MVL4.all; + +architecture gate_level of misc_logic is + + signal src1, src1_enable : MVL4_ulogic; + signal src2, src2_enable : MVL4_ulogic; + signal selected_val : MVL4_logic; + -- . . . + +begin + + src1_buffer : entity work.tri_state_buffer(behavioral) + port map ( a => src1, enable => src1_enable, y => selected_val ); + + src2_buffer : entity work.tri_state_buffer(behavioral) + port map ( a => src2, enable => src2_enable, y => selected_val ); + + -- . . . + + -- not in book + + stimulus : process is + begin + wait for 10 ns; + src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns; + src1 <= '0'; src2 <= '1'; wait for 10 ns; + src1_enable <= '1'; wait for 10 ns; + src1 <= 'Z'; wait for 10 ns; + src1 <= '1'; wait for 10 ns; + src1_enable <= '0'; wait for 10 ns; + src2_enable <= '1'; wait for 10 ns; + src2 <= 'Z'; wait for 10 ns; + src2 <= '0'; wait for 10 ns; + src2_enable <= '0'; wait for 10 ns; + src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns; + src1 <= '0'; wait for 10 ns; + src1 <= 'X'; wait for 10 ns; + src1 <= '1'; src2 <= '1'; wait for 10 ns; + + wait; + end process stimulus; + + -- end not in book + +end architecture gate_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd new file mode 100644 index 000000000..233339aaf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity resolve_tri_state_logic is +end entity resolve_tri_state_logic; + + + +architecture test of resolve_tri_state_logic is + + -- code from book (in text) + + type tri_state_logic is ('0', '1', 'Z'); + + type tri_state_logic_array is array (integer range <>) of tri_state_logic; + + -- end code from book + + + -- code from book + + function resolve_tri_state_logic ( values : in tri_state_logic_array ) + return tri_state_logic is + variable result : tri_state_logic := 'Z'; + begin + for index in values'range loop + if values(index) /= 'Z' then + result := values(index); + end if; + end loop; + return result; + end function resolve_tri_state_logic; + + -- end code from book + + + -- code from book (in text) + + signal s1 : resolve_tri_state_logic tri_state_logic; + + subtype resolved_logic is resolve_tri_state_logic tri_state_logic; + + signal s2, s3 : resolved_logic; + + -- end code from book + +begin + + source_1 : s1 <= 'Z', + '0' after 10 ns, + 'Z' after 20 ns, + '1' after 30 ns, + 'Z' after 40 ns, + '1' after 200 ns, + 'Z' after 220 ns; + + source_2 : s1 <= 'Z', + '0' after 110 ns, + 'Z' after 120 ns, + '1' after 130 ns, + 'Z' after 140 ns, + '1' after 200 ns, + '0' after 210 ns, + 'Z' after 220 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd new file mode 100644 index 000000000..21db85828 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package resolved is + + type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); + type std_ulogic_vector is array ( natural range <> ) of std_ulogic; + function resolved ( s : std_ulogic_vector ) return std_ulogic; + +end package resolved; + + +package body resolved is + + -- code from book + + type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic; + constant resolution_table : stdlogic_table := + -- --------------------------------------------- + -- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' + -- --------------------------------------------- + ( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- 'U' + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- 'X' + ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- '0' + ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- '1' + ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- 'Z' + ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- 'W' + ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- 'L' + ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- 'H' + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- '-' + ); + + function resolved ( s : std_ulogic_vector ) return std_ulogic is + variable result : std_ulogic := 'Z'; -- weakest state default + begin + if s'length = 1 then + return s(s'low); + else + for i in s'range loop + result := resolution_table(result, s(i)); + end loop; + end if; + return result; + end function resolved; + + -- end code from book + +end package body resolved; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd new file mode 100644 index 000000000..1591023e6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +package synchronize is + + procedure init_synchronize ( signal synch : out std_logic ); + + procedure begin_synchronize ( signal synch : inout std_logic; + Tdelay : in delay_length := 0 fs ); + + procedure end_synchronize ( signal synch : inout std_logic; + Tdelay : in delay_length := 0 fs ); + +end package synchronize; + + + +package body synchronize is + + -- code from book + + procedure init_synchronize ( signal synch : out std_logic ) is + begin + synch <= '0'; + end procedure init_synchronize; + + procedure begin_synchronize ( signal synch : inout std_logic; + Tdelay : in delay_length := 0 fs ) is + begin + synch <= 'Z' after Tdelay; + wait until synch = 'H'; + end procedure begin_synchronize; + + procedure end_synchronize ( signal synch : inout std_logic; + Tdelay : in delay_length := 0 fs ) is + begin + synch <= '0' after Tdelay; + wait until synch = '0'; + end procedure end_synchronize; + + -- end code from book + +end package body synchronize; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd new file mode 100644 index 000000000..99649caf4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd @@ -0,0 +1,66 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity synchronized_module is +end entity synchronized_module; + + + +architecture test of synchronized_module is + + use work.synchronize.all; + + signal barrier : std_logic; + +begin + + pullup : barrier <= 'H'; + + -- code from book + + synchronized_module : process is + -- . . . + begin + init_synchronize(barrier); + -- . . . + loop + -- . . . + begin_synchronize(barrier); + -- . . . -- perform operation, synchronized with other processes + end_synchronize(barrier); + -- . . . + end loop; + end process synchronized_module; + + -- end code from book + + another_synchronized_module : process is + begin + init_synchronize(barrier); + loop + wait for 10 ns; + begin_synchronize(barrier); + -- . . . -- perform operation, synchronized with other processes + end_synchronize(barrier); + end loop; + end process another_synchronized_module; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd new file mode 100644 index 000000000..a4b3d1d19 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd @@ -0,0 +1,35 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +use work.MVL4.all; + +entity tri_state_buffer is + port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic ); +end entity tri_state_buffer; + +-------------------------------------------------- + +architecture behavioral of tri_state_buffer is +begin + + y <= 'Z' when enable = '0' else + a when enable = '1' and (a = '0' or a = '1') else + 'X'; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd new file mode 100644 index 000000000..d5ccffc72 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package words is + + type X01Z is ('X', '0', '1', 'Z'); + type uword is array (0 to 31) of X01Z; + + type uword_vector is array (natural range <>) of uword; + + function resolve_word ( contribution : uword_vector ) return uword; + + subtype word is resolve_word uword; + + -- not in book + type ubyte is array (0 to 7) of X01Z; + -- end not in book + +end package words; + +-------------------------------------------------- + +package body words is + + type table is array (X01Z, X01Z) of X01Z; + + constant resolution_table : table := + -- 'X' '0' '1' 'Z' + -- ------------------ + ( ( 'X', 'X', 'X', 'X' ), -- 'X' + ( 'X', '0', 'X', '0' ), -- '0' + ( 'X', 'X', '1', '1' ), -- '1' + ( 'X', '0', '1', 'Z' ) ); -- 'Z' + + function resolve_word ( contribution : uword_vector ) return uword is + variable result : uword := (others => 'Z'); + begin + for index in contribution'range loop + for element in uword'range loop + result(element) := + resolution_table( result(element), contribution(index)(element) ); + end loop; + end loop; + return result; + end function resolve_word; + +end package body words; |