diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks')
24 files changed, 1605 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd new file mode 100644 index 000000000..c4707cdcb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd @@ -0,0 +1,60 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity circuit is + generic ( inpad_delay, outpad_delay : delay_length ); + port ( in1, in2, in3 : in bit; out1, out2 : out bit ); +end entity circuit; + +-------------------------------------------------- + +architecture with_pad_delays of circuit is + + component subcircuit is + port ( a, b : in bit; y1, y2 : out bit ); + end component subcircuit; + + signal delayed_in1, delayed_in2, delayed_in3 : bit; + signal undelayed_out1, undelayed_out2 : bit; + +begin + + input_delays : block is + begin + delayed_in1 <= in1 after inpad_delay; + delayed_in2 <= in2 after inpad_delay; + delayed_in3 <= in3 after inpad_delay; + end block input_delays; + + functionality : block is + signal intermediate : bit; + begin + cell1 : component subcircuit + port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate ); + cell2 : component subcircuit + port map ( intermediate, delayed_in3, undelayed_out2, open ); + end block functionality; + + output_delays : block is + begin + out1 <= undelayed_out1 after outpad_delay; + out2 <= undelayed_out2 after outpad_delay; + end block output_delays; + +end architecture with_pad_delays; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd new file mode 100644 index 000000000..dded8af1b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd @@ -0,0 +1,99 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity computer_system_abstract is +end entity computer_system_abstract; + + +-- code from book + +architecture abstract of computer_system_abstract is + + -- not in book + + subtype word is bit_vector(31 downto 0); + type word_vector is array (natural range <>) of word; + + function resolve_word ( drivers : word_vector ) return word is + begin + if drivers'length > 0 then + return drivers(drivers'left); + else + return X"00000000"; + end if; + end function resolve_word; + + -- end not in book + + -- . . . + + signal address_bus : resolve_word word bus; + signal hold_req : bit; + -- . . . + + -- not in book + signal clk : bit := '0'; + -- end not in book + +begin + + cpu : block is + + signal guard : boolean := false; + signal cpu_internal_address : word; + -- . . . + + begin + + cpu_address_driver: + address_bus <= guarded cpu_internal_address; + + -- . . . -- other bus drivers + + controller : process is + -- . . . + begin + -- . . . + -- . . . -- determine when to disable cpu bus drivers + guard <= false; + wait on clk until hold_req = '0' and clk = '1'; + guard <= true; -- reenable cpu bus drivers + -- . . . + -- not in book + wait until clk = '1'; + -- end not in book + end process controller; + + -- . . . -- cpu data-path processes + + -- not in book + cpu_internal_address <= X"11111111"; + -- end not in book + + end block cpu; + + -- . . . -- blocks for DMA and other modules + + -- not in book + clk <= '1' after 10 ns, '0' after 20 ns when clk = '0'; + -- end not in book + +end architecture abstract; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd new file mode 100644 index 000000000..8b71df4f9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity computer_system is +end entity computer_system; + +-- end not in book + + +architecture top_level of computer_system is + + function resolve_bits ( bits : bit_vector ) return bit is + variable result : bit := '0'; + begin + for index in bits'range loop + result := result or bits(index); + exit when result = '1'; + end loop; + return result; + end function resolve_bits; + + signal write_en : resolve_bits bit bus; + -- . . . + + -- not in book + constant Tpd : delay_length := 2 ns; + signal clock, hold_req : bit := '0'; + -- end not in book + +begin + + CPU : process is + -- . . . + begin + write_en <= '0' after Tpd; + -- . . . + loop + wait until clock = '1'; + if hold_req = '1' then + write_en <= null after Tpd; + wait on clock until clock = '1' and hold_req = '0'; + write_en <= '0' after Tpd; + end if; + -- . . . + end loop; + end process CPU; + + -- . . . + + -- not in book + + clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0'; + + stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns; + + process is + begin + write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns; + wait; + end process; + + -- end not in book + +end architecture top_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd new file mode 100644 index 000000000..22a42dfb9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd @@ -0,0 +1,95 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity data_logger is +end entity data_logger; + + +-- code from book + +architecture high_level of data_logger is + + subtype byte is bit_vector(7 downto 0); + + type byte_array is array (integer range <>) of byte; + + function resolver ( bytes : byte_array ) return byte is + begin + if bytes'length > 0 then + return bytes( bytes'left ); + else + return X"00"; + end if; + end function resolver; + + subtype resolved_byte is resolver byte; + + procedure reg ( signal clock, out_enable : in bit; + signal d : in byte; + signal q : out resolved_byte ) is + variable stored_byte : byte; + begin + loop + if clock = '1' then + stored_byte := d; + end if; + if out_enable = '1' then + q <= stored_byte; + else + q <= null; + end if; + wait on clock, out_enable, d; + end loop; + end procedure reg; + + signal data_bus : resolved_byte bus; + -- . . . + + -- not in book + signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0'; + signal port_a, port_b : byte := X"00"; + -- end not in book + +begin + + a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus); + + b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus); + + -- . . . + + -- not in book + + stimulus : process is + begin + port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns; + a_reg_read <= '1', '0' after 5 ns; wait for 10 ns; + port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns; + b_reg_read <= '1', '0' after 5 ns; wait for 10 ns; + a_reg_read <= '1', '0' after 5 ns; + b_reg_read <= '1', '0' after 5 ns; + + wait; + end process stimulus; + + -- end not in book + +end architecture high_level; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd new file mode 100644 index 000000000..819d6e43b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity example_entity is +end entity example_entity; + +-- end not in book + + +architecture contrived of example_entity is + + constant sig_width : positive := 16; + signal s1, s2, s3 : bit_vector (0 to sig_width - 1); + signal sel : bit; + -- . . . + +begin + + mux : block is + generic ( width : positive ); + generic map ( width => sig_width ); + port ( d0, d1 : in bit_vector(0 to width - 1); + y : out bit_vector(0 to width - 1); + sel : in bit); + port map ( d0 => s1, d1=> s2, y => s3, sel => sel ); + + constant zero : bit_vector(0 to width - 1) := ( others => '0' ); + signal gated_d0, gated_d1 : bit_vector(0 to width - 1); + + begin + gated_d0 <= d0 when sel = '0' else zero; + gated_d1 <= d1 when sel = '1' else zero; + y <= gated_d0 or gated_d1; + end block mux; + + -- . . . + + -- not in book + + stimulus : process is + begin + s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns; + s1 <= X"0101"; wait for 10 ns; + s2 <= X"0202"; wait for 10 ns; + sel <= '1'; wait for 10 ns; + s1 <= X"0001"; wait for 10 ns; + s2 <= X"0002"; wait for 10 ns; + + wait; + end process stimulus; + + -- end not in book + +end architecture contrived; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd new file mode 100644 index 000000000..bb46694b4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity real_subcircuit is + port ( a, b : in bit; y1, y2 : out bit ); +end entity real_subcircuit; + + +architecture basic of real_subcircuit is +begin + y1 <= a and b after 10 ns; + y2 <= a nand b after 10 ns; +end architecture basic; + + + +-- code from book + +configuration full of circuit is + + for with_pad_delays -- configure the architecture + + for functionality -- configure the block + + for all : subcircuit + use entity work.real_subcircuit(basic); + end for; + + end for; + + end for; + +end configuration full; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt new file mode 100644 index 000000000..fa600e31d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt @@ -0,0 +1,34 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 19 - Guards and Blocks +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +computer_system.vhd entity computer_system top_level Figure 19-1 +processor.vhd entity processor rtl Figure 19-2 +resolve.vhd package resolve body Section 19.1, Figure 19-4 +tri_state_reg.vhd entity tri_state_reg behavioral Section 19.1, Figure 19-5 +data_logger.vhd entity data_logger high_level Figure 19-6 +reg_read_selector.vhd entity reg_read_selector test Figure 19-7 +processor_node.vhd entity processor_node dataflow Figure 19-8 +latch.vhd entity latch behavioral Figure 19-9 +computer_system-1.vhd entity computer_system_abstract abstract Figure 19-10 +sensor.vhd entity sensor detailed_timing Figures 19-12, 19-13 +example_entity.vhd entity example_entity contrived Figure 19-14 +circuit.vhd entity circuit with_pad_delays Figure 19-15 +full.vhd entity real_subcircuit basic -- +-- configuration full -- Figure 19-16 +inline_01.vhd entity inline_01 test Section 19.1 +inline_02.vhd entity inline_02 test Section 19.1 +inline_03.vhd entity inline_03 test Section 19.1 +inline_04.vhd entity inline_04 test Section 19.2 +inline_05.vhd entity inline_05 test Section 19.2 +inline_06.vhd entity inline_06 test Section 19.2 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_tri_state_reg.vhd entity tb_tri_state_reg test tri_state_reg.vhd +tb_latch.vhd entity tb_latch test latch.vhd +tb_sensor.vhd entity tb_sensor tb_sensor sensor.vhd +tb_full.vhd entity tb_full test full.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd new file mode 100644 index 000000000..27b98a66e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd @@ -0,0 +1,60 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_01 is + +end entity inline_01; + + +---------------------------------------------------------------- + + +architecture test of inline_01 is + + function pulled_up ( drivers : bit_vector ) return bit is + begin + for index in drivers'range loop + if drivers(index) = '0' then + return '0'; + end if; + end loop; + return '1'; + end function pulled_up; + + type state_type is (init_state, state1, state2, state3); + type state_vector is array (integer range <>) of state_type; + + function resolve_state ( drivers : state_vector ) return state_type is + begin + return drivers(drivers'left); + end function resolve_state; + + + -- code from book: + + signal interrupt_request : pulled_up bit bus; + + signal stored_state : resolve_state state_type register := init_state; + + -- end of code from book + +begin + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd new file mode 100644 index 000000000..1a2c612bf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_02 is + +end entity inline_02; + + +---------------------------------------------------------------- + + +architecture test of inline_02 is + + -- code from book: + + subtype word is bit_vector(0 to 31); + type word_array is array (integer range <>) of word; + + function resolve_words ( words : word_array ) return word; + + signal s : resolve_words word bus; + + -- end of code from book + + function resolve_words ( words : word_array ) return word is + begin + if words'length > 0 then + return words(words'left); + else + return X"00000000"; + end if; + end function resolve_words; + + constant T_delay : delay_length := 2 ns; + +begin + + + process is + begin + + -- code from book (should fail) + + s(0 to 15) <= X"003F" after T_delay; + s(16 to 31) <= null after T_delay; + + -- end of code from book + + wait; + end process; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd new file mode 100644 index 000000000..a1498abec --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_03 is + +end entity inline_03; + + +---------------------------------------------------------------- + + +architecture test of inline_03 is + + function pulled_up ( drivers : bit_vector ) return bit is + begin + for index in drivers'range loop + if drivers(index) = '0' then + return '0'; + end if; + end loop; + return '1'; + end function pulled_up; + + signal s : pulled_up bit bus; + +begin + + + process is + begin + + s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns, + null after 19 ns, '0' after 25 ns; + wait for 10 ns; + + -- code from book: + + s <= reject 3 ns inertial null after 10 ns; + + -- end of code from book + + wait; + end process; + + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd new file mode 100644 index 000000000..eefda275e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_04 is + +end entity inline_04; + + +---------------------------------------------------------------- + + +architecture test of inline_04 is + + subtype word is bit_vector(0 to 31); + type word_array is array (integer range <>) of word; + + function resolve_words ( words : word_array ) return word is + begin + if words'length > 0 then + return words(words'left); + else + return X"00000000"; + end if; + end function resolve_words; + + subtype resolved_word is resolve_words word; + + -- code from book: + + signal memory_data_bus : resolved_word bus; + disconnect memory_data_bus : resolved_word after 3 ns; + + -- end of code from book + + signal mem_sel, mem_write : boolean; + signal cache_data_bus : word; + +begin + + + -- code from book: + + mem_write_buffer : block (mem_sel and mem_write) is + begin + memory_data_bus <= + guarded reject 2 ns inertial cache_data_bus after 4 ns; + end block mem_write_buffer; + + -- end of code from book + + stimulus : process is + begin + cache_data_bus <= X"DDDDDDDD"; + wait for 10 ns; + mem_sel <= true; mem_write <= true; + wait for 10 ns; + cache_data_bus <= X"AAAAAAAA"; + wait for 10 ns; + mem_sel <= false; mem_write <= false; + wait for 10 ns; + cache_data_bus <= X"11111111"; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd new file mode 100644 index 000000000..578845470 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd @@ -0,0 +1,78 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_05 is + +end entity inline_05; + + +architecture test of inline_05 is + + subtype word is bit_vector(0 to 31); + type word_array is array (integer range <>) of word; + + function resolve_words ( words : word_array ) return word is + begin + if words'length > 0 then + return words(words'left); + else + return X"00000000"; + end if; + end function resolve_words; + + subtype resolved_word is resolve_words word; + + -- code from book: + + signal source_bus_1, source_bus_2 : resolved_word bus; + signal address_bus : resolved_word bus; + + disconnect all : resolved_word after 2 ns; + + -- end of code from book + + signal s : word; + signal g : boolean; + +begin + + + b : block (g) is + begin + source_bus_1 <= guarded s after 4 ns; + source_bus_2 <= guarded s after 4 ns; + address_bus <= guarded s after 4 ns; + end block b; + + stimulus : process is + begin + s <= X"DDDDDDDD"; + wait for 10 ns; + g <= true; + wait for 10 ns; + s <= X"AAAAAAAA"; + wait for 10 ns; + g <= false; + wait for 10 ns; + s <= X"11111111"; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd new file mode 100644 index 000000000..00534b5c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd @@ -0,0 +1,83 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_06 is + +end entity inline_06; + + +---------------------------------------------------------------- + + +architecture test of inline_06 is + + subtype word is bit_vector(0 to 31); + type word_array is array (integer range <>) of word; + + function resolve_words ( words : word_array ) return word is + begin + if words'length > 0 then + return words(words'left); + else + return X"00000000"; + end if; + end function resolve_words; + + subtype resolved_word is resolve_words word; + + signal source_bus_1, source_bus_2 : resolved_word bus; + signal address_bus : resolved_word bus; + + -- code from book: + + disconnect address_bus : resolved_word after 3 ns; + + disconnect others : resolved_word after 2 ns; + + -- end of code from book + + signal s : word; + signal g : boolean; + +begin + + + b : block (g) is + begin + source_bus_1 <= guarded s after 4 ns; + source_bus_2 <= guarded s after 4 ns; + address_bus <= guarded s after 4 ns; + end block b; + + stimulus : process is + begin + s <= X"DDDDDDDD"; + wait for 10 ns; + g <= true; + wait for 10 ns; + s <= X"AAAAAAAA"; + wait for 10 ns; + g <= false; + wait for 10 ns; + s <= X"11111111"; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd new file mode 100644 index 000000000..aaceb5c4e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity latch is + generic ( width : positive ); + port ( enable : in bit; + d : in bit_vector(0 to width - 1); + q : out bit_vector(0 to width - 1) ); +end entity latch; + +-------------------------------------------------- + +architecture behavioral of latch is +begin + + transfer_control : block ( enable = '1' ) is + begin + q <= guarded d; + end block transfer_control; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd new file mode 100644 index 000000000..412f9e368 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd @@ -0,0 +1,101 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity processor is +end entity processor; + + + +-- code from book + +architecture rtl of processor is + + subtype word is bit_vector(0 to 31); + type word_vector is array (natural range <>) of word; + + function resolve_unique ( drivers : word_vector ) return word is + begin + return drivers(drivers'left); + end function resolve_unique; + + signal source1, source2 : resolve_unique word register; + -- . . . + + -- not in book + + type alu_op_type is (pass1, pass2, add, subtract); + + procedure perform_alu_op ( signal alu_opcode : in alu_op_type; + signal source1, source2 : in word; + signal destination : out word; + constant ignored : in integer := 0 ) is + begin + null; + end procedure perform_alu_op; + + signal phase1, source1_reg_out_en,other_signal : bit; + signal alu_opcode : alu_op_type; + signal destination : word; + + -- end not in book + +begin + + source1_reg : process (phase1, source1_reg_out_en, -- . . .) is + -- not in book + other_signal) is + -- end not in book + variable stored_value : word; + begin + -- . . . + if source1_reg_out_en = '1' and phase1 = '1' then + source1 <= stored_value; + -- not in book + stored_value := not stored_value; + -- end not in book + else + source1 <= null; + end if; + end process source1_reg; + + alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . ); + -- not in book + open ); + -- end not in book + + -- . . . + + -- not in book + + process is + begin + wait for 10 ns; + source1_reg_out_en <= '1'; + phase1 <= '1', '0' after 10 ns; + wait for 20 ns; + source1_reg_out_en <= '1'; + phase1 <= '1', '0' after 10 ns; + wait; + end process; + + -- end not in book + +end architecture rtl; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd new file mode 100644 index 000000000..20c782792 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd @@ -0,0 +1,91 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity processor_node is +end entity processor_node; + + +-- code from book + +architecture dataflow of processor_node is + + -- not in book + + subtype word is bit_vector(31 downto 0); + type word_vector is array (natural range <>) of word; + + function resolve_unique ( drivers : word_vector ) return word is + begin + if drivers'length > 0 then + return drivers(drivers'left); + else + return X"00000000"; + end if; + end function resolve_unique; + + -- end not in book + + signal address_bus : resolve_unique word bus; + -- . . . + + -- not in book + signal cache_miss, dirty, replace_section, + snoop_hit, flag_update : bit := '0'; + constant tag_section0 : bit_vector(11 downto 0) := X"000"; + constant tag_section1 : bit_vector(11 downto 0) := X"001"; + constant set_index : bit_vector(15 downto 0) := X"6666"; + constant snoop_address : word := X"88888888"; + -- end not in book + +begin + + cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is + begin + address_bus <= guarded + tag_section0 & set_index & B"0000" when replace_section = '0' else + tag_section1 & set_index & B"0000"; + end block cache_to_address_buffer; + + snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is + begin + address_bus <= guarded snoop_address(31 downto 4) & B"0000"; + end block snoop_to_address_buffer; + + -- . . . + + -- not in book + + stimulus : process is + begin + wait for 10 ns; + dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns; + dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns; + replace_section <= '1'; + cache_miss <= '1', '0' after 5 ns; wait for 10 ns; + flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns; + flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns; + + wait; + end process stimulus; + + -- end not in book + +end architecture dataflow; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd new file mode 100644 index 000000000..569fe0384 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity reg_read_selector is +end entity reg_read_selector; + + +architecture test of reg_read_selector is + + constant reg0 : std_logic_vector(7 downto 0) := "00000000"; + constant reg1 : std_logic_vector(7 downto 0) := "11111111"; + signal dbus : std_logic_vector(7 downto 0); + signal reg_sel, read, reg_addr : X01 := '0'; + +begin + + -- code from book + + reg_read_selector : block (reg_sel = '1' and read = '1') is + begin + dbus <= reg0 when guard and reg_addr = '0' else + reg1 when guard and reg_addr = '1' else + "ZZZZZZZZ"; + end block reg_read_selector; + + -- end code from book + + stimulus : process is + begin + reg_sel <= '1'; wait for 10 ns; + read <= '1', '0' after 5 ns; wait for 10 ns; + reg_sel <= '0'; wait for 10 ns; + read <= '1', '0' after 5 ns; wait for 10 ns; + reg_addr <= '1'; wait for 10 ns; + reg_sel <= '1'; wait for 10 ns; + read <= '1', '0' after 5 ns; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd new file mode 100644 index 000000000..4cdeeb52f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package resolve is + + -- code from book (in text) + + subtype byte is bit_vector(0 to 7); + type byte_array is array (integer range <>) of byte; + function resolve ( bytes : byte_array ) return byte; + subtype resolved_byte is resolve byte; + + -- end code from book + +end package resolve; + + +package body resolve is + + -- code from book + + function resolve ( bytes : byte_array ) return byte is + variable result : byte := b"0000_0000"; + begin + for index in bytes'range loop + result := result or bytes(index); + end loop; + return result; + end function resolve; + + -- end code from book + +end package body resolve; + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd new file mode 100644 index 000000000..1a27df3fc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd @@ -0,0 +1,62 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity sensor is + + generic ( threshold : real; -- voltage threshold + tipd_clk : delay_length; -- input prop delay on clk + tipd_input : real; -- input prop delay on sensor input + topd_q : delay_length ); -- output prop delay on q + + port ( terminal input : electrical; -- sensor analog input + signal clk : in bit; -- edge–triggered clock input + signal q : out bit ); -- sensor digital output + +end entity sensor; + + +architecture detailed_timing of sensor is + + quantity vin across input; -- analog input values + quantity v_delayed : voltage; -- input voltage delayed + signal clk_delayed : bit; -- clk input port delayed + signal q_int : bit; -- q output with zero delay + +begin + + input_port_delay : block is + begin + v_delayed == vin'delayed(tipd_input); + clk_delayed <= clk'delayed(tipd_clk); + end block input_port_delay; + + AD_conversion : block is + begin + q_int <= '1' when vin'above(threshold) else + '0'; + end block AD_conversion; + + output_port_delay : block is + begin + q <= q_int'delayed(topd_q); + end block output_port_delay; + +end architecture detailed_timing; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd new file mode 100644 index 000000000..bc6300a9d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_full is +end entity tb_full; + + +library util; use util.stimulus_generators.all; + +architecture test of tb_full is + + signal in1, in2, in3, out1, out2 : bit; + signal test_vector : bit_vector(1 to 3); + +begin + + dut : configuration work.full + generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns ) + port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 ); + + stimulus : all_possible_values ( test_vector, 50 ns ); + + (in1, in2, in3) <= test_vector; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd new file mode 100644 index 000000000..e6fb12f09 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd @@ -0,0 +1,47 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_latch is +end entity tb_latch; + + +architecture test of tb_latch is + + signal enable : bit := '0'; + signal d, q : bit_vector(0 to 7); + +begin + + dut : entity work.latch(behavioral) + generic map ( width => 8 ) + port map ( enable => enable, d => d, q => q ); + + stimulus : process is + begin + wait for 10 ns; + d <= X"11"; wait for 10 ns; + enable <= '1'; wait for 10 ns; + d <= X"AA"; wait for 10 ns; + enable <= '0'; wait for 10 ns; + d <= X"00"; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd new file mode 100644 index 000000000..de3d13094 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd @@ -0,0 +1,84 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; +use IEEE_proposed.mechanical_systems.all; + +entity tb_sensor is +end tb_sensor; + +architecture tb_sensor of tb_sensor is + -- Component declarations + -- Signal declarations + terminal vin : electrical; + signal clk, q : bit; + signal lclclkinitwire : bit := '0'; +begin + -- Signal assignments + -- Component instances + v1 : entity work.v_sine(ideal) + generic map( + freq => 10.0, + amplitude => 1.0 + ) + port map( + pos => vin, + neg => electrical_ref + ); + sens1 : entity work.sensor_wa(detailed_timing) + generic map( + threshold => 0.25, + tipd_clk => 10 ns, + tipd_input => 20.0e-9, + topd_q => 10 ns + ) + port map( + input => vin, + clk => clk, + q => q + ); + -- ctrl + P_ctrl : + process + begin + if (lclclkinitwire /= '1') + then + clk <= '0'; + wait for 1000.000 ns; + else + clk <= '1'; + wait for 5240.000 ns; + clk <= '0'; + wait for 34760.000 ns; + end if; + end process P_ctrl; + + KillerProc : + process + begin + wait for 1 ns; + lclclkinitwire <= '1'; + wait; + end process; +end tb_sensor; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd new file mode 100644 index 000000000..993cdf4ca --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +use work.resolve.all; + +entity tb_tri_state_reg is +end entity tb_tri_state_reg; + + +architecture test of tb_tri_state_reg is + + signal d1, d2, q : resolved_byte := X"00"; + signal clk1, clk2, oe1, oe2 : bit := '0'; + +begin + + dut1 : entity work.tri_state_reg(behavioral) + port map ( d => d1, q => q, clock => clk1, out_enable => oe1 ); + + dut2 : entity work.tri_state_reg(behavioral) + port map ( d => d2, q => q, clock => clk2, out_enable => oe2 ); + + stimulus : process is + begin + d1 <= X"11"; clk1 <= '1', '0' after 5 ns; wait for 10 ns; + oe1 <= '1', '0' after 5 ns; wait for 10 ns; + d2 <= X"21"; clk2 <= '1', '0' after 5 ns; wait for 10 ns; + oe2 <= '1', '0' after 5 ns; wait for 10 ns; + oe1 <= '1', '0' after 5 ns; + oe2 <= '1', '0' after 5 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd new file mode 100644 index 000000000..8c0bd7a6a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +use work.resolve.all; + +-- code from book (in text) + +entity tri_state_reg is + port ( d : in resolved_byte; + q : out resolved_byte bus; + clock, out_enable : in bit ); +end entity tri_state_reg; + +-- end code from book + + + +-- code from book + +architecture behavioral of tri_state_reg is +begin + + reg_behavior : process (d, clock, out_enable) is + variable stored_byte : byte; + begin + if clock'event and clock = '1' then + stored_byte := d; + end if; + if out_enable = '1' then + q <= stored_byte; + else + q <= null; + end if; + end process reg_behavior; + +end architecture behavioral; + +-- end code from book |